| 12400871 |
Metal lines with low via-to-via spacing |
Somnath Ghosh, Hsueh-Chung Chen, Carl Radens, Lawrence A. Clevenger |
2025-08-26 |
| 12363965 |
Stacked transistor layout for improved cell height scaling |
Ruilong Xie, Nicholas Anthony Lanzillo, Albert M. Chu, Eric Miller, Lawrence A. Clevenger |
2025-07-15 |
| 12080559 |
Using a same mask for direct print and self-aligned double patterning of nanosheets |
Stuart A. Sieg, Eric R. Miller |
2024-09-03 |
| 12068415 |
Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance |
Kai Zhao, Shahab Siddiqui, Rishikesh Krishnan, Charlotte DeWan Adams |
2024-08-20 |
| 11977614 |
Circuit design watermarking |
Carl Radens, Lawrence A. Clevenger, Hsueh-Chung Chen |
2024-05-07 |
| 11888048 |
Gate oxide for nanosheet transistor devices |
Shahab Siddiqui, Koji Watanabe, Charlotte DeWan Adams, Kai Zhao, Rishikesh Krishnan |
2024-01-30 |
| 11830778 |
Back-side wafer modification |
David Wolpert, Lawrence A. Clevenger, Michael Romain, Somnath Ghosh |
2023-11-28 |
| 11527434 |
Line cut patterning using sacrificial material |
Timothy Mathew Philip, Somnath Ghosh, Robert R. Robison |
2022-12-13 |
| 11515427 |
Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance |
Kai Zhao, Shahab Siddiqui, Rishikesh Krishnan, Charlotte DeWan Adams |
2022-11-29 |
| 11257681 |
Using a same mask for direct print and self-aligned double patterning of nanosheets |
Stuart A. Sieg, Eric R. Miller |
2022-02-22 |
| 11211474 |
Gate oxide for nanosheet transistor devices |
Shahab Siddiqui, Koji Watanabe, Charlotte DeWan Adams, Kai Zhao, Rishikesh Krishnan |
2021-12-28 |
| 11158536 |
Patterning line cuts before line patterning using sacrificial fill material |
Timothy Mathew Philip, Somnath Ghosh, Robert R. Robison |
2021-10-26 |
| 11024551 |
Metal replacement vertical interconnections for buried capacitance |
Hsueh-Chung Chen, Lawrence A. Clevenger, Somnath Ghosh, Carl Radens |
2021-06-01 |
| 10998193 |
Spacer-assisted lithographic double patterning |
Timothy Mathew Philip, Somnath Ghosh, Robert R. Robison, Lawrence A. Clevenger |
2021-05-04 |
| 10867912 |
Dummy fill scheme for use with passive devices |
Jaladhi Mehta, Brian J. Greene, Ahmed Hassan |
2020-12-15 |
| 10833160 |
Field-effect transistors with self-aligned and non-self-aligned contact openings |
Michael V. Aquilino, Daniel Jaeger, Naved Siddiqui, Jessica Dechene, Shreesh Narasimha +1 more |
2020-11-10 |
| 10691862 |
Layouts for connecting contacts with metal tabs or vias |
Neha Nayyar, David Pritchard, George J. Kluth |
2020-06-23 |
| 10332745 |
Dummy assist features for pattern support |
Lei Sun, Ruilong Xie, Wenhui Wang, Yulu Chen, Erik Verduijn +2 more |
2019-06-25 |
| 10217633 |
Substantially defect-free polysilicon gate arrays |
Heng Yang, Ahmed Hassan |
2019-02-26 |
| 10170309 |
Dummy pattern addition to improve CD uniformity |
Geng Han |
2019-01-01 |
| 9780002 |
Threshold voltage and well implantation method for semiconductor devices |
Xintuo Dai, Brian J. Greene, Mahender Kumar, Daniel Jaeger |
2017-10-03 |
| 9252022 |
Patterning assist feature to mitigate reactive ion etch microloading effect |
Geng Han, Scott M. Mansfield, Stuart A. Sieg, Yunpeng Yin |
2016-02-02 |
| 8656322 |
Fin design level mask decomposition for directed self assembly |
Michael A. Guillorn, Kafai Lai, Jed W. Pitera, HsinYu Tsai |
2014-02-18 |
