Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12068415 | Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance | Kai Zhao, Shahab Siddiqui, Daniel James Dechene, Rishikesh Krishnan | 2024-08-20 |
| 11888048 | Gate oxide for nanosheet transistor devices | Shahab Siddiqui, Koji Watanabe, Kai Zhao, Daniel James Dechene, Rishikesh Krishnan | 2024-01-30 |
| 11515427 | Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance | Kai Zhao, Shahab Siddiqui, Daniel James Dechene, Rishikesh Krishnan | 2022-11-29 |
| 11211474 | Gate oxide for nanosheet transistor devices | Shahab Siddiqui, Koji Watanabe, Kai Zhao, Daniel James Dechene, Rishikesh Krishnan | 2021-12-28 |
| 10755918 | Spacer with laminate liner | Man Gu, Tao Han | 2020-08-25 |
| 10192791 | Semiconductor devices with robust low-k sidewall spacers and method for producing the same | Man Gu, Tao Han, Junsic Hong, Jiehui Shu, Asli Sirman +2 more | 2019-01-29 |
| 9087722 | Semiconductor devices having different gate oxide thicknesses | Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui | 2015-07-21 |
| 8941177 | Semiconductor devices having different gate oxide thicknesses | Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui | 2015-01-27 |
| 8030709 | Metal gate stack and semiconductor gate stack for CMOS devices | Bruce B. Doris, Philip A. Fisher, William K. Henson, Jeffrey W. Sleight | 2011-10-04 |
| 7230336 | Dual damascene copper interconnect to a damascene tungsten wiring level | Anthony K. Stamper | 2007-06-12 |
| 6566242 | Dual damascene copper interconnect to a damascene tungsten wiring level | Anthony K. Stamper | 2003-05-20 |