Issued Patents All Time
Showing 25 most recent of 289 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12166106 | Graphene/nanostructure FET with self-aligned contact and gate | Josephine B. Chang, Isaac Lauer | 2024-12-10 |
| 12041856 | Superconducting circuit provided on an encapsulated vacuum cavity | Isaac Lauer, Karthik Balakrishnan, David J. Frank | 2024-07-16 |
| 11678591 | Vacuum encapsulated Josephson junction | Isaac Lauer, Karthik Balakrishnan, David J. Frank | 2023-06-13 |
| 11538977 | Qubits with ion implant Josephson junctions | Ryan T. Gordon, Kenneth P. Rodbell, Robert L. Sandstrom | 2022-12-27 |
| 10699955 | Techniques for creating a local interconnect using a SOI wafer | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2020-06-30 |
| 10580894 | Strained semiconductor nanowire | Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin | 2020-03-03 |
| 10366892 | Hybrid III-V technology to support multiple supply voltages and off state currents on same chip | Josephine B. Chang, Isaac Lauer, Amlan Majumdar | 2019-07-30 |
| 10361219 | Implementing a hybrid finFET device and nanowire device utilizing selective SGOI | Josephine B. Chang, Leland Chang, Isaac Lauer | 2019-07-23 |
| 10354960 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Isaac Lauer, Tenko Yamashita | 2019-07-16 |
| 10170679 | Josephson junction with spacer | Josephine B. Chang, Michael A. Guillorn, Ryan M. Martin | 2019-01-01 |
| 10170634 | Wire-last gate-all-around nanowire FET | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2019-01-01 |
| 10056293 | Techniques for creating a local interconnect using a SOI wafer | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2018-08-21 |
| 10056487 | Strained semiconductor nanowire | Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin | 2018-08-21 |
| 9997472 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Isaac Lauer, Tenko Yamashita | 2018-06-12 |
| 9960233 | Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor | Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan | 2018-05-01 |
| 9954063 | Stacked planar double-gate lamellar field-effect transistor | Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer | 2018-04-24 |
| 9954062 | Stacked planar double-gate lamellar field-effect transistor | Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer | 2018-04-24 |
| 9929334 | Josephson junction with spacer | Josephine B. Chang, Michael A. Guillorn, Ryan M. Martin | 2018-03-27 |
| 9922942 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Isaac Lauer, Tenko Yamashita | 2018-03-20 |
| 9922830 | Hybrid III-V technology to support multiple supply voltages and off state currents on same chip | Josephine B. Chang, Isaac Lauer, Amlan Majumdar | 2018-03-20 |
| 9917057 | Mixed lithography approach for E-beam and optical exposure using HSQ | Josephine B. Chang, Szu-Lin Cheng, Isaac Lauer | 2018-03-13 |
| 9859430 | Local germanium condensation for suspended nanowire and finFET devices | Josephine B. Chang, Leland Chang, Isaac Lauer | 2018-01-02 |
| 9859375 | Stacked planar double-gate lamellar field-effect transistor | Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer | 2018-01-02 |
| 9812370 | III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology | Josephine B. Chang, Gen P. Lauer, Isaac Lauer | 2017-11-07 |
| 9754965 | Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2017-09-05 |