Issued Patents All Time
Showing 26–50 of 289 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9728624 | Semiconductor testing devices | Josephine B. Chang, Isaac Lauer, Tenko Yamashita | 2017-08-08 |
| 9728619 | Generation of multiple diameter nanowire field effect transistors | Sarunya Bangsaruntip, Guy M. Cohen | 2017-08-08 |
| 9691715 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Isaac Lauer, Tenko Yamashita | 2017-06-27 |
| 9684753 | Techniques for generating nanowire pad data from pre-existing design data | Karthik Balakrishnan, Josephine B. Chang, Michael A. Guillorn | 2017-06-20 |
| 9660027 | Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor | Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan | 2017-05-23 |
| 9627330 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Isaac Lauer, Tenko Yamashita | 2017-04-18 |
| 9627508 | Replacement channel TFET | Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan | 2017-04-18 |
| 9601576 | Nanowire FET with tensile channel stressor | Isaac Lauer, Chung-Hsun Lin | 2017-03-21 |
| 9570563 | III-V compound and Germanium compound nanowire suspension with Germanium-containing release layer | Guy M. Cohen, Isaac Lauer, Alexander Reznicek | 2017-02-14 |
| 9564514 | Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels | Anirban Basu, Amlan Majumdar | 2017-02-07 |
| 9564502 | Techniques for multiple gate workfunctions for a nanowire CMOS technology | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2017-02-07 |
| 9558930 | Mixed lithography approach for e-beam and optical exposure using HSQ | Josephine B. Chang, Szu-Lin Cheng, Isaac Lauer | 2017-01-31 |
| 9548381 | Method and structure for III-V nanowire tunnel FETs | Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan | 2017-01-17 |
| 9543388 | Complementary metal-oxide silicon having silicon and silicon germanium channels | Gen P. Lauer, Isaac Lauer, Alexander Reznicek | 2017-01-10 |
| 9536885 | Hybrid FINFET/nanowire SRAM cell using selective germanium condensation | Josephine B. Chang, Leland Chang, Isaac Lauer | 2017-01-03 |
| 9536794 | Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2017-01-03 |
| 9530860 | III-V MOSFETs with halo-doped bottom barrier layer | Pranita Kerber, Chung-Hsun Lin, Amlan Majumdar | 2016-12-27 |
| 9530876 | Strained semiconductor nanowire | Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin | 2016-12-27 |
| 9514937 | Tapered nanowire structure with reduced off current | Sarunya Bangsaruntip | 2016-12-06 |
| 9496184 | III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology | Josephine B. Chang, Gen P. Lauer, Isaac Lauer | 2016-11-15 |
| 9496338 | Wire-last gate-all-around nanowire FET | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2016-11-15 |
| 9483592 | Maintaining stress in a layout design of an integrated circuit having fin-type field-effect transistor devices | Karthik Balakrishnan, Pouya Hashemi, Tenko Yamashita | 2016-11-01 |
| 9472658 | III-V nanowire FET with compositionally-graded channel and wide-bandgap core | Anirban Basu, Guy M. Cohen, Amlan Majumdar | 2016-10-18 |
| 9466673 | Complementary metal-oxide silicon having silicon and silicon germanium channels | Gen P. Lauer, Isaac Lauer, Alexander Reznicek | 2016-10-11 |
| 9449820 | Epitaxial growth techniques for reducing nanowire dimension and pitch | Guy M. Cohen, Michael A. Guillorn, Isaac Lauer | 2016-09-20 |