Issued Patents All Time
Showing 25 most recent of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12166260 | Embedded microstrip transmission line | William Francis Landers, Srikanth Srinivasan, Neereja Sundaresan | 2024-12-10 |
| 12166106 | Graphene/nanostructure FET with self-aligned contact and gate | Jeffrey W. Sleight, Josephine B. Chang | 2024-12-10 |
| 12147300 | Pulsed stark tones for collision mitigation | Neereja Sundaresan, Emily Pritchett | 2024-11-19 |
| 12041856 | Superconducting circuit provided on an encapsulated vacuum cavity | Karthik Balakrishnan, Jeffrey W. Sleight, David J. Frank | 2024-07-16 |
| 11789812 | Pulsed stark tones for collision mitigation | Neereja Sundaresan, Emily Pritchett | 2023-10-17 |
| 11751491 | Heavy-hex connection topology to rectilinear physical layout | Neereja Sundaresan | 2023-09-05 |
| 11695483 | Target qubit decoupling in an echoed cross-resonance gate | Neereja Sundaresan | 2023-07-04 |
| 11678591 | Vacuum encapsulated Josephson junction | Karthik Balakrishnan, Jeffrey W. Sleight, David J. Frank | 2023-06-13 |
| 11625638 | Drive enhanced J/ZZ operation for superconducting qubits | Abhinav Kandala, David C. Mckay, Easwar Magesan | 2023-04-11 |
| 11586448 | Qubit reset from excited states | Oliver Dial, Matthias Steffen | 2023-02-21 |
| 11526796 | Qubit pulse calibration via canary parameter monitoring | — | 2022-12-13 |
| 11469485 | Embedded microstrip transmission line | William Francis Landers, Srikanth Srinivasan, Neereja Sundaresan | 2022-10-11 |
| 11223347 | All microwave ZZ control | David C. Mckay, Abhinav Kandala, Oliver Dial, Matthias Steffen | 2022-01-11 |
| 11069775 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETS | Josephine B. Chang, Michael A. Guillorn, Xin Miao | 2021-07-20 |
| 11004933 | Field effect transistor structures | Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2021-05-11 |
| 11004678 | Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer | Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2021-05-11 |
| 10699955 | Techniques for creating a local interconnect using a SOI wafer | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2020-06-30 |
| 10680061 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs | Josephine B. Chang, Michael A. Guillorn, Xin Miao | 2020-06-09 |
| 10658461 | Nanowire with sacrificial top wire | Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2020-05-19 |
| 10580894 | Strained semiconductor nanowire | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2020-03-03 |
| 10573714 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs | Josephine B. Chang, Michael A. Guillorn, Xin Miao | 2020-02-25 |
| 10522342 | Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer | Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2019-12-31 |
| 10395922 | Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer | Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2019-08-27 |
| 10366892 | Hybrid III-V technology to support multiple supply voltages and off state currents on same chip | Josephine B. Chang, Amlan Majumdar, Jeffrey W. Sleight | 2019-07-30 |
| 10367062 | Co-integration of silicon and silicon-germanium channels for nanosheet devices | Michael A. Guillorn, Nicolas Loubet | 2019-07-30 |