Issued Patents All Time
Showing 51–75 of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9887264 | Nanowire field effect transistor (FET) and method for fabricating the same | Jack O. Chu, Szu-Lin Cheng, Kuen-Ting Shiu, Jeng-Bang Yau | 2018-02-06 |
| 9859430 | Local germanium condensation for suspended nanowire and finFET devices | Josephine B. Chang, Leland Chang, Jeffrey W. Sleight | 2018-01-02 |
| 9859375 | Stacked planar double-gate lamellar field-effect transistor | Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Jeffrey W. Sleight | 2018-01-02 |
| 9812370 | III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology | Josephine B. Chang, Gen P. Lauer, Jeffrey W. Sleight | 2017-11-07 |
| 9812321 | Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure | Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2017-11-07 |
| 9793398 | Fabrication of a strained region on a substrate | Jiaxing Liu, Renee T. Mo | 2017-10-17 |
| 9755017 | Co-integration of silicon and silicon-germanium channels for nanosheet devices | Michael A. Guillorn, Nicolas Loubet | 2017-09-05 |
| 9754965 | Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2017-09-05 |
| 9748348 | Fully-depleted SOI MOSFET with U-shaped channel | Takashi Ando, Robert H. Dennard, Ramachandran Muralidhar | 2017-08-29 |
| 9748404 | Method for fabricating a semiconductor device including gate-to-bulk substrate isolation | Josephine B. Chang, Michael A. Guillorn, Xin Miao | 2017-08-29 |
| 9728624 | Semiconductor testing devices | Josephine B. Chang, Jeffrey W. Sleight, Tenko Yamashita | 2017-08-08 |
| 9691715 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Tenko Yamashita, Jeffrey W. Sleight | 2017-06-27 |
| 9653547 | Integrated etch stop for capped gate and method for manufacturing the same | Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2017-05-16 |
| 9647139 | Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer | Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2017-05-09 |
| 9627378 | Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding | Takashi Ando, Robert H. Dennard, Ramachandran Muralidhar, Ghavam G. Shahidi | 2017-04-18 |
| 9627330 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Tenko Yamashita, Jeffrey W. Sleight | 2017-04-18 |
| 9601576 | Nanowire FET with tensile channel stressor | Chung-Hsun Lin, Jeffrey W. Sleight | 2017-03-21 |
| 9589791 | Compound finFET device including oxidized III-V fin isolator | Szu-Lin Cheng, Kuen-Ting Shiu, Jeng-Bang Yau | 2017-03-07 |
| 9570563 | III-V compound and Germanium compound nanowire suspension with Germanium-containing release layer | Guy M. Cohen, Alexander Reznicek, Jeffrey W. Sleight | 2017-02-14 |
| 9564502 | Techniques for multiple gate workfunctions for a nanowire CMOS technology | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2017-02-07 |
| 9564500 | Fully-depleted SOI MOSFET with U-shaped channel | Takashi Ando, Robert H. Dennard, Ramachandran Muralidhar | 2017-02-07 |
| 9558930 | Mixed lithography approach for e-beam and optical exposure using HSQ | Josephine B. Chang, Szu-Lin Cheng, Jeffrey W. Sleight | 2017-01-31 |
| 9548355 | Compound finFET device including oxidized III-V fin isolator | Szu-Lin Cheng, Kuen-Ting Shiu, Jeng-Bang Yau | 2017-01-17 |
| 9548238 | Method of manufacturing a semiconductor device using a self-aligned OPL replacement contact and patterned HSQ and a semiconductor device formed by same | Szu-Lin Cheng, Jack O. Chu, Jeng-Bang Yau | 2017-01-17 |
| 9543388 | Complementary metal-oxide silicon having silicon and silicon germanium channels | Gen P. Lauer, Alexander Reznicek, Jeffrey W. Sleight | 2017-01-10 |