Issued Patents All Time
Showing 76–100 of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9536885 | Hybrid FINFET/nanowire SRAM cell using selective germanium condensation | Josephine B. Chang, Leland Chang, Jeffrey W. Sleight | 2017-01-03 |
| 9536794 | Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2017-01-03 |
| 9530876 | Strained semiconductor nanowire | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2016-12-27 |
| 9496184 | III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology | Josephine B. Chang, Gen P. Lauer, Jeffrey W. Sleight | 2016-11-15 |
| 9496338 | Wire-last gate-all-around nanowire FET | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2016-11-15 |
| 9466673 | Complementary metal-oxide silicon having silicon and silicon germanium channels | Gen P. Lauer, Alexander Reznicek, Jeffrey W. Sleight | 2016-10-11 |
| 9449820 | Epitaxial growth techniques for reducing nanowire dimension and pitch | Guy M. Cohen, Michael A. Guillorn, Jeffrey W. Sleight | 2016-09-20 |
| 9443949 | Techniques for multiple gate workfunctions for a nanowire CMOS technology | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2016-09-13 |
| 9437613 | Multiple VT in III-V FETs | Josephine B. Chang, Amlan Majumdar, Jeffrey W. Sleight | 2016-09-06 |
| 9431301 | Nanowire field effect transistor (FET) and method for fabricating the same | Jack O. Chu, Szu-Lin Cheng, Kuen-Ting Shiu, Jeng-Bang Yau | 2016-08-30 |
| 9391163 | Stacked planar double-gate lamellar field-effect transistor | Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Jeffrey W. Sleight | 2016-07-12 |
| 9390980 | III-V compound and germanium compound nanowire suspension with germanium-containing release layer | Guy M. Cohen, Alexander Reznicek, Jeffrey W. Sleight | 2016-07-12 |
| 9385122 | Method of manufacturing a semiconductor device using source/drain epitaxial overgrowth for forming self-aligned contacts without spacer loss and a semiconductor device formed by same | Szu-Lin Cheng, Jack O. Chu, Jeng-Bang Yau | 2016-07-05 |
| 9373638 | Complementary metal-oxide silicon having silicon and silicon germanium channels | Gen P. Lauer, Alexander Reznicek, Jeffrey W. Sleight | 2016-06-21 |
| 9368599 | Graphene/nanostructure FET with self-aligned contact and gate | Josephine B. Chang, Jeffrey W. Sleight | 2016-06-14 |
| 9362354 | Tuning gate lengths in semiconductor device structures | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2016-06-07 |
| 9324801 | Nanowire FET with tensile channel stressor | Chung-Hsun Lin, Jeffrey W. Sleight | 2016-04-26 |
| 9299615 | Multiple VT in III-V FETs | Josephine B. Chang, Amlan Majumdar, Jeffrey W. Sleight | 2016-03-29 |
| 9287136 | FinFET field-effect transistors with atomic layer doping | Kevin K. Chan, Young-Hee Kim, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang +1 more | 2016-03-15 |
| 9281397 | Semiconductor device including an asymmetric feature | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2016-03-08 |
| 9263550 | Gate to diffusion local interconnect scheme using selective replacement gate flow | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2016-02-16 |
| 9240326 | Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact | Szu-Lin Cheng, Jack O. Chu, Jeng-Bang Yau | 2016-01-19 |
| 9224604 | Device and method for forming sharp extension region with controllable junction depth and lateral overlap | Effendi Leobandung, Ghavam G. Shahidi | 2015-12-29 |
| 9209095 | III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method | Josephine B. Chang, Gen P. Lauer, Jeffrey W. Sleight | 2015-12-08 |
| 9209086 | Low temperature salicide for replacement gate nanowires | Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Jeffrey W. Sleight | 2015-12-08 |