Issued Patents All Time
Showing 26–50 of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10361219 | Implementing a hybrid finFET device and nanowire device utilizing selective SGOI | Josephine B. Chang, Leland Chang, Jeffrey W. Sleight | 2019-07-23 |
| 10361304 | Fabrication of a strained region on a substrate | Jiaxing Liu, Renee T. Mo | 2019-07-23 |
| 10354960 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Tenko Yamashita, Jeffrey W. Sleight | 2019-07-16 |
| 10325983 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs | Josephine B. Chang, Michael A. Guillorn, Xin Miao | 2019-06-18 |
| 10217817 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs | Josephine B. Chang, Michael A. Guillorn, Xin Miao | 2019-02-26 |
| 10170609 | Internal spacer formation from selective oxidation for Fin-first wire-last replacement gate-all-around nanowire FET | Szu-Lin Cheng, Michael A. Guillorn, Gen P. Lauer | 2019-01-01 |
| 10170552 | Co-integration of silicon and silicon-germanium channels for nanosheet devices | Michael A. Guillorn, Nicolas Loubet | 2019-01-01 |
| 10170636 | Gate-to-bulk substrate isolation in gate-all-around devices | Josephine B. Chang, Michael A. Guillorn, Xin Miao | 2019-01-01 |
| 10170634 | Wire-last gate-all-around nanowire FET | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2019-01-01 |
| 10170608 | Internal spacer formation from selective oxidation for fin-first wire-last replacement gate-all-around nanowire FET | Szu-Lin Cheng, Michael A. Guillorn, Gen P. Lauer | 2019-01-01 |
| 10121786 | FinFET with U-shaped channel and S/D epitaxial cladding extending under gate spacers | Takashi Ando, Robert H. Dennard, Ramachandran Muralidhar, Ghavam G. Shahidi | 2018-11-06 |
| 10096673 | Nanowire with sacrificial top wire | Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2018-10-09 |
| 10056487 | Strained semiconductor nanowire | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2018-08-21 |
| 10056293 | Techniques for creating a local interconnect using a SOI wafer | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2018-08-21 |
| 10050144 | Fabrication of a strained region on a substrate | Jiaxing Liu, Renee T. Mo | 2018-08-14 |
| 10037885 | Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer | Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2018-07-31 |
| 10026810 | Co-integration of silicon and silicon-germanium channels for nanosheet devices | Michael A. Guillorn, Nicolas Loubet | 2018-07-17 |
| 9997613 | Integrated etch stop for capped gate and method for manufacturing the same | Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2018-06-12 |
| 9997472 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Tenko Yamashita, Jeffrey W. Sleight | 2018-06-12 |
| 9954063 | Stacked planar double-gate lamellar field-effect transistor | Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Jeffrey W. Sleight | 2018-04-24 |
| 9954062 | Stacked planar double-gate lamellar field-effect transistor | Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Jeffrey W. Sleight | 2018-04-24 |
| 9922942 | Support for long channel length nanowire transistors | Karthik Balakrishnan, Tenko Yamashita, Jeffrey W. Sleight | 2018-03-20 |
| 9922830 | Hybrid III-V technology to support multiple supply voltages and off state currents on same chip | Josephine B. Chang, Amlan Majumdar, Jeffrey W. Sleight | 2018-03-20 |
| 9917057 | Mixed lithography approach for E-beam and optical exposure using HSQ | Josephine B. Chang, Szu-Lin Cheng, Jeffrey W. Sleight | 2018-03-13 |
| 9911592 | Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure | Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2018-03-06 |