RM

Renee T. Mo

IBM: 96 patents #604 of 70,183Top 1%
FS Freeescale Semiconductor: 1 patents #2,021 of 3,767Top 55%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
Overall (All Time): #15,177 of 4,157,543Top 1%
98
Patents All Time

Issued Patents All Time

Showing 25 most recent of 98 patents

Patent #TitleCo-InventorsDate
11018225 III-V extension by high temperature plasma doping Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Christopher Scerbo, Hongwen Yan +1 more 2021-05-25
10930565 III-V CMOS co-integration HsinYu Tsai, Cheng-Wei Cheng, Ko-Tao Lee 2021-02-23
10763340 Growing Groups III-V lateral nanowire channels Sanghoon Lee, Effendi Leobandung, Brent A. Wacaser 2020-09-01
10672671 Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap Takashi Ando, Martin M. Frank, Vijay Narayanan 2020-06-02
10593600 Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap Takashi Ando, Martin M. Frank, Vijay Narayanan 2020-03-17
10580686 Semiconductor structure with integrated passive structures Anthony I. Chou, Arvind Kumar, Shreesh Narasimha 2020-03-03
10553584 Patterned gate dielectrics for III-V-based CMOS circuits Takashi Ando, Martin M. Frank, Vijay Narayanan, John Rozen 2020-02-04
10504799 Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap Takashi Ando, Martin M. Frank, Vijay Narayanan 2019-12-10
10396077 Patterned gate dielectrics for III-V-based CMOS circuits Takashi Ando, Martin M. Frank, Vijay Narayanan, John Rozen 2019-08-27
10361304 Fabrication of a strained region on a substrate Isaac Lauer, Jiaxing Liu 2019-07-23
10246745 DNA sequencing detection field effect transistor Sanghoon Lee, Effendi Leobandung 2019-04-02
10242906 Semiconductor structure with integrated passive structures Anthony I. Chou, Arvind Kumar, Shreesh Narasimha 2019-03-26
10205003 Surface roughness of III-V fin formed on silicon sidewall by implementing sacrificial buffers Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung 2019-02-12
10109737 Method of forming high-germanium content silicon germanium alloy fins on insulator Pouya Hashemi, John A. Ott, Alexander Reznicek 2018-10-23
10103242 Growing groups III-V lateral nanowire channels Sanghoon Lee, Effendi Leobandung, Brent A. Wacaser 2018-10-16
10083987 CMOS with middle of line processing of III-V material on mandrel Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung 2018-09-25
10083986 CMOS with middle of line processing of III-V material on mandrel Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung 2018-09-25
10062693 Patterned gate dielectrics for III-V-based CMOS circuits Takashi Ando, Martin M. Frank, Vijay Narayanan, John Rozen 2018-08-28
10062694 Patterned gate dielectrics for III-V-based CMOS circuits Takashi Ando, Martin M. Frank, Vijay Narayanan, John Rozen 2018-08-28
10050144 Fabrication of a strained region on a substrate Isaac Lauer, Jiaxing Liu 2018-08-14
10037989 III-V lateral bipolar integration with silicon Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung 2018-07-31
10032862 Semiconductor structure with integrated passive structures Anthony I. Chou, Arvind Kumar, Shreesh Narasimha 2018-07-24
9988678 DNA sequencing detection field effect transistor Sanghoon Lee, Effendi Leobandung 2018-06-05
9859397 Growing groups III-V lateral nanowire channels Sanghoon Lee, Effendi Leobandung, Brent A. Wacaser 2018-01-02
9793398 Fabrication of a strained region on a substrate Isaac Lauer, Jiaxing Liu 2017-10-17