Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12048254 | Sacrificial material facilitating protection of a substrate in a qubit device | Vivekananda P. Adiga, Martin O. Sandberg, Jeng-Bang Yau, David L. Rath, John Bruley +2 more | 2024-07-23 |
| 11882771 | Smooth metal layers in Josephson junction devices | Kathryn Jessica Pooley, Gerald W. Gibson | 2024-01-23 |
| 11844290 | Plasma co-doping to reduce the forming voltage in resistive random access memory (ReRAM) devices | Devi Koty, Qingyun Yang, Hiroyuki Miyazoe, Takashi Ando, Marinus Hopstaken | 2023-12-12 |
| 11575077 | Microfabricated air bridges for quantum circuits | Vivekananda P. Adiga, John M. Papalia, David L. Rath, Jyotica V. Patel | 2023-02-07 |
| 11018225 | III-V extension by high temperature plasma doping | Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Renee T. Mo, Christopher Scerbo +1 more | 2021-05-25 |
| 10366918 | Self-aligned trench metal-alloying for III-V nFETs | Kevin K. Chan, Sebastian U. Engelmann, Marinus Hopstaken, Christopher Scerbo, Yu Zhu | 2019-07-30 |
| 10276384 | Plasma shallow doping and wet removal of depth control cap | Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Dario L. Goldfarb, Marinus Hopstaken +3 more | 2019-04-30 |
| 9240452 | Array and moat isolation structures and method of manufacture | Naoyoshi Kusaba, Oh-Jung Kwon, Zhengwen Li | 2016-01-19 |
| 9087927 | Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches | Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-Jung Kwon +1 more | 2015-07-21 |
| 8907405 | Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures | Reinaldo Vega | 2014-12-09 |
| 8901706 | Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches | Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-Jung Kwon +1 more | 2014-12-02 |
| 8785281 | CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials | Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-Yung Sung +2 more | 2014-07-22 |
| 8673737 | Array and moat isolation structures and method of manufacture | Naoyoshi Kusaba, Oh-Jung Kwon, Zhengwen Li | 2014-03-18 |
| 8481389 | Method of removing high-K dielectric layer on sidewalls of gate structure | Ying Zhang, Qingyun Yang | 2013-07-09 |
| 8227874 | Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes | James W. Adkisson, Michael P. Chudzik, Jeffrey P. Gambino | 2012-07-24 |
| 8198103 | Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist | Timothy J. Dalton, Wesley C. Natzle, Paul W. Pastel, Richard S. Wise, Ying Zhang | 2012-06-12 |
| 8193099 | Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing | Mukesh V. Khare, Renee T. Mo, Ravikumar Ramachandran, Richard S. Wise | 2012-06-05 |
| 8158481 | CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials | Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-Yung Sung +2 more | 2012-04-17 |
| 8159040 | Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor | Douglas D. Coolbaugh, Ebenezer E. Eshun, Ephrem G. Gebreselasie, Zhong-Xiang He, Herbert L. Ho +8 more | 2012-04-17 |
| 8018005 | CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs | Bruce B. Doris, William K. Henson, Richard S. Wise | 2011-09-13 |
| 7863124 | Residue free patterned layer formation method applicable to CMOS structures | Michael P. Chudzik, Bruce B. Doris, William K. Henson, Ying Zhang | 2011-01-04 |
| 7863123 | Direct contact between high-κ/metal gate and wiring process flow | Huiming Bu, Michael P. Chudzik, Ricardo A. Donaton, Naim Moumen | 2011-01-04 |
| 7820552 | Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack | Siva Kanakasabapathy, Ying Zhang, Edmund M. Sikorski, Vijay Narayanan, Vamsi K. Paruchuri +1 more | 2010-10-26 |
| 7820555 | Method of patterning multilayer metal gate structures for CMOS devices | Bruce B. Doris, Richard S. Wise, Ying Zhang | 2010-10-26 |
| 7790559 | Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes | James W. Adkisson, Michael P. Chudzik, Jeffrey P. Gambino | 2010-09-07 |