Issued Patents All Time
Showing 25 most recent of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11048174 | Method of controlling a patterning process, lithographic apparatus, metrology apparatus lithographic cell and associated computer program | Michael Kubis, Marinus Jochemsen, Nader Shamma, Girish Dixit, Liesbeth REIJNEN +3 more | 2021-06-29 |
| 10651286 | High selectivity nitride removal process based on selective polymer deposition | Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C. M. Fuller, Masahiro Nakamura | 2020-05-12 |
| 10573526 | Method of charge controlled patterning during reactive ion etching | Sunit S. Mahajan, Bachir Dirahoui | 2020-02-25 |
| 10546743 | Advanced interconnect with air gap | John H. Zhang, Yann Mignot, Lawrence A. Clevenger, Carl Radens, Yiheng Xu +2 more | 2020-01-28 |
| 10325998 | High selectivity nitride removal process based on selective polymer deposition | Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C. M. Fuller, Masahiro Nakamura | 2019-06-18 |
| 10269924 | High selectivity nitride removal process based on selective polymer deposition | Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C. M. Fuller, Masahiro Nakamura | 2019-04-23 |
| 9786551 | Trench structure for high performance interconnection lines of different resistivity and method of making same | John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu | 2017-10-10 |
| 9709898 | Amplification method for photoresist exposure in semiconductor chip manufacturing | Daniel A. Corliss | 2017-07-18 |
| 9691900 | Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch | Kangguo Cheng, Ali Khakifirooz | 2017-06-27 |
| 9680015 | Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch | Kangguo Cheng, Ali Khakifirooz | 2017-06-13 |
| 9659820 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Akil Khamisi Sutton +2 more | 2017-05-23 |
| 9658523 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Terry A. Spooner +1 more | 2017-05-23 |
| 9627533 | High selectivity nitride removal process based on selective polymer deposition | Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C. M. Fuller, Masahiro Nakamura | 2017-04-18 |
| 9577068 | Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation | Gregory Costrini, Ravikumar Ramachandran, Reinaldo Vega | 2017-02-21 |
| 9530665 | Protective trench layer and gate spacer in finFET devices | Effendi Leobandung | 2016-12-27 |
| 9514992 | Unidirectional spacer in trench silicide | Emre Alptekin, Sameer H. Jain, Unoh Kwon, Zhengwen Li, Hari V. Mallela +3 more | 2016-12-06 |
| 9496148 | Method of charge controlled patterning during reactive ion etching | Sunit S. Mahajan, Bachir Dirahoui | 2016-11-15 |
| 9431395 | Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation | Gregory Costrini, Ravikumar Ramachandran, Reinaldo Vega | 2016-08-30 |
| 9412654 | Graphene sacrificial deposition layer on beol copper liner-seed for mitigating queue-time issues between liner and plating step | Junjing Bao, Lawrence A. Clevenger, Vincent J. McGahay, Joyeeta Nag, Yiheng Xu | 2016-08-09 |
| 9391020 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Akil Khamisi Sutton +2 more | 2016-07-12 |
| 9324793 | Method for controlling the profile of an etched metallic layer | Lawrence A. Clevenger, Carl Radens, Edem Wornyo, Yiheng Xu, John H. Zhang | 2016-04-26 |
| 9236447 | Asymmetric spacers | Kangguo Cheng, Ali Khakifirooz | 2016-01-12 |
| 9214429 | Trench interconnect having reduced fringe capacitance | John H. Zhang, Hsueh-Chung Chen, Lawrence A. Clevenger, Yann Mignot, Carl Radens +2 more | 2015-12-15 |
| 9214541 | Self-aligned contact for replacement gate devices | Ravikumar Ramachandran, Ying Li | 2015-12-15 |
| 9209036 | Method for controlling the profile of an etched metallic layer | Lawrence A. Clevenger, Carl Radens, Edem Wornyo, Yiheng Xu, John H. Zhang | 2015-12-08 |