Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10741554 | Third type of metal gate stack for CMOS devices | Ramachandra Divakaruni, Viraj Y. Sardesai, Keith H. Tabakman | 2020-08-11 |
| 10262996 | Third type of metal gate stack for CMOS devices | Ramachandra Divakaruni, Viraj Y. Sardesai, Keith H. Tabakman | 2019-04-16 |
| 9875939 | Methods of forming uniform and pitch independent fin recess | Yue Ke, Alexander Reznicek, Benjamin G. Moser, Dominic J. Schepis, Melissa A. Smith +2 more | 2018-01-23 |
| 9679993 | Fin end spacer for preventing merger of raised active regions | Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran, Reinaldo Vega | 2017-06-13 |
| 9634006 | Third type of metal gate stack for CMOS devices | Ramachandra Divakaruni, Viraj Y. Sardesai, Keith H. Tabakman | 2017-04-25 |
| 9601380 | Fin end spacer for preventing merger of raised active regions | Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran, Reinaldo Vega | 2017-03-21 |
| 9514992 | Unidirectional spacer in trench silicide | Emre Alptekin, Unoh Kwon, Zhengwen Li, Hari V. Mallela, Ayse M. Ozbek +3 more | 2016-12-06 |
| 9515168 | Fin end spacer for preventing merger of raised active regions | Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran, Reinaldo Vega | 2016-12-06 |
| 9391175 | Fin end spacer for preventing merger of raised active regions | Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran, Reinaldo Vega | 2016-07-12 |
| 9349836 | Fin end spacer for preventing merger of raised active regions | Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran, Reinaldo Vega | 2016-05-24 |
| 9331166 | Selective dielectric spacer deposition for exposing sidewalls of a finFET | Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran, Reinaldo Vega | 2016-05-03 |
| 9111962 | Selective dielectric spacer deposition for exposing sidewalls of a finFET | Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran, Reinaldo Vega | 2015-08-18 |
| 8951868 | Formation of functional gate structures with different critical dimensions using a replacement gate process | — | 2015-02-10 |
| 8652914 | Two-step silicide formation | Emre Alptekin, Reinaldo Vega | 2014-02-18 |
| 8647954 | Two-step silicide formation | Emre Alptekin, Reinaldo Vega | 2014-02-11 |
| 8642424 | Replacement metal gate structure and methods of manufacture | Jeffrey B. Johnson, Ying Li, Hasan M. Nayfeh, Ravikumar Ramachandran | 2014-02-04 |
| 8629510 | Two-step silicide formation | Emre Alptekin, Reinaldo Vega | 2014-01-14 |
| 8421077 | Replacement gate MOSFET with self-aligned diffusion contact | Carl Radens, Shahab Siddiqui, Jay William Strane | 2013-04-16 |
| 8236637 | Planar silicide semiconductor structure | Henry K. Utomo, Ravikumar Ramachandran, Cung D. Tran | 2012-08-07 |
| 7687338 | Method of reducing embedded SiGe loss in semiconductor device manufacturing | Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Jang Sim | 2010-03-30 |
| 7615435 | Semiconductor device and method of manufacture | Oleg Gluschenkov, Yaocheng Liu | 2009-11-10 |
| 7538339 | Scalable strained FET device and method of fabricating the same | Brian J. Greene, William K. Henson | 2009-05-26 |