Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11081583 | FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth | Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Henry K. Utomo | 2021-08-03 |
| 10991796 | Source/drain contact depth control | Lin Hu, Veeraraghavan S. Basker, Brian J. Greene, Kai Zhao, Daniel Jaeger +1 more | 2021-04-27 |
| 10978566 | Middle of line structures | Hui Zang, Guowei Xu, Viraj Sardesai | 2021-04-13 |
| 10825811 | Gate cut first isolation formation with contact forming process mask protection | Xiaoming Yang, Sipeng Gu, Jeffrey Chee | 2020-11-03 |
| 10741554 | Third type of metal gate stack for CMOS devices | Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai | 2020-08-11 |
| 10734233 | FinFET with high-k spacer and self-aligned contact capping layer | Hui Zang, Guowei Xu | 2020-08-04 |
| 10635007 | Apparatus and method for aligning integrated circuit layers using multiple grating materials | Dongyue Yang, Guanchen He, Xintuo Dai, Xueli Hao | 2020-04-28 |
| 10615279 | FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth | Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Henry K. Utomo | 2020-04-07 |
| 10580875 | Middle of line structures | Hui Zang, Guowei Xu, Viraj Sardesai | 2020-03-03 |
| 10297504 | Methods of forming a gate structure-to-source/drain conductive contact and the resulting devices | Hui Zang, Ruilong Xie | 2019-05-21 |
| 10262996 | Third type of metal gate stack for CMOS devices | Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai | 2019-04-16 |
| 10243077 | FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth | Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Henry K. Utomo | 2019-03-26 |
| 10192791 | Semiconductor devices with robust low-k sidewall spacers and method for producing the same | Man Gu, Tao Han, Junsic Hong, Jiehui Shu, Asli Sirman +2 more | 2019-01-29 |
| 10049985 | Contact line having insulating spacer therein and method of forming same | Veeraraghavan S. Basker, Patrick Carpenter, Guillaume Bouche, Michael V. Aquilino | 2018-08-14 |
| 9917190 | FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth | Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Henry K. Utomo | 2018-03-13 |
| 9831123 | Methods of forming MIS contact structures on transistor devices | Suraj K. Patil, Zhiguo Sun | 2017-11-28 |
| 9812400 | Contact line having insulating spacer therein and method of forming same | Veeraraghavan S. Basker, Patrick Carpenter, Guillaume Bouche, Michael V. Aquilino | 2017-11-07 |
| 9634006 | Third type of metal gate stack for CMOS devices | Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai | 2017-04-25 |
| 9613855 | Methods of forming MIS contact structures on transistor devices in CMOS applications | Suraj K. Patil, Zhiguo Sun | 2017-04-04 |
| 9536900 | Forming fins of different semiconductor materials on the same substrate | Ravikumar Ramachandran, Huiling Shang, Henry K. Utomo, Reinaldo Vega | 2017-01-03 |
| 9312364 | finFET with dielectric isolation after gate module for improved source and drain region epitaxial growth | Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Henry K. Utomo | 2016-04-12 |
| 9293593 | Self aligned device with enhanced stress and methods of manufacture | Judson R. Holt, Viorel Ontalus | 2016-03-22 |
| 9171800 | Electrical fuse with bottom contacts | Lawrence A. Clevenger, Zhengwen Li, Dan Moy, Viraj Y. Sardesai | 2015-10-27 |
| 9059286 | Pre-gate, source/drain strain layer formation | Judson R. Holt, Viorel Ontalus | 2015-06-16 |
| 9006052 | Self aligned device with enhanced stress and methods of manufacture | Judson R. Holt, Viorel Ontalus | 2015-04-14 |