Issued Patents All Time
Showing 25 most recent of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12336206 | Heterojunction bipolar transistors with a cut stress liner | Vibhor Jain, Jeffrey B. Johnson, John J. Pekarik | 2025-06-17 |
| 12113070 | Transistor integration on a silicon-on-insulator substrate | Peter Baars, Ketankumar Harishbhai Tailor, Michael Zier, Crystal R. Kenney, Judson R. Holt | 2024-10-08 |
| 11916135 | Bipolar transistor | Justin C. Long, Robert K. Baiocco | 2024-02-27 |
| 11810951 | Semiconductor-on-insulator field effect transistor with performance-enhancing source/drain shapes and/or materials | Jianwei Peng, Hong Yu | 2023-11-07 |
| 11728380 | Bipolar transistor with base horizontally displaced from collector | — | 2023-08-15 |
| 11588043 | Bipolar transistor with elevated extrinsic base and methods to form same | Judson R. Holt | 2023-02-21 |
| 11404563 | Insulated-gate bipolar transistor with enhanced frequency response, and related methods | — | 2022-08-02 |
| 11217685 | Heterojunction bipolar transistor with marker layer | Herbert L. Ho, Vibhor Jain, John J. Pekarik, Claude Ortolland, Judson R. Holt +1 more | 2022-01-04 |
| 11056533 | Bipolar junction transistor device with piezoelectric material positioned adjacent thereto | — | 2021-07-06 |
| 10374090 | Replacement body FinFET for improved junction profile with gate self-aligned junctions | — | 2019-08-06 |
| 9953873 | Methods of modulating the morphology of epitaxial semiconductor material | Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Christopher D. Sheraw, Timothy J. McArdle +1 more | 2018-04-24 |
| 9761720 | Replacement body FinFET for improved junction profile with gate self-aligned junctions | — | 2017-09-12 |
| 9722045 | Buffer layer for modulating Vt across devices | Bhupesh Chandra, Timothy J. McArdle, Paul Chang, Claude Ortolland, Judson R. Holt | 2017-08-01 |
| 9673295 | Contact resistance optimization via EPI growth engineering | Annie Levesque, Matthew W. Stoker | 2017-06-06 |
| 9536989 | Field-effect transistors with source/drain regions of reduced topography | Annie Levesque | 2017-01-03 |
| 9385237 | Source and drain doping profile control employing carbon-doped semiconductor material | Pranita Kerber, Donald R. Wall, Zhengmao Zhu | 2016-07-05 |
| 9349749 | Semiconductor device including SIU butted junction to reduce short-channel penalty | Robert R. Robison, Xin-Yong WANG | 2016-05-24 |
| 9293593 | Self aligned device with enhanced stress and methods of manufacture | Judson R. Holt, Keith H. Tabakman | 2016-03-22 |
| 9287399 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt +6 more | 2016-03-15 |
| 9231108 | Source and drain doping profile control employing carbon-doped semiconductor material | Pranita Kerber, Donald R. Wall, Zhengmao Zhu | 2016-01-05 |
| 9171844 | Gate structures and methods of manufacture | Unoh Kwon, Ramachandran Muralidhar | 2015-10-27 |
| 9165944 | Semiconductor device including SOI butted junction to reduce short-channel penalty | Robert R. Robison, Xin-Yong WANG | 2015-10-20 |
| 9105718 | Butted SOI junction isolation structures and devices and method of fabrication | Jeffrey B. Johnson, Shreesh Narasimha, Hasan M. Nayfeh, Robert R. Robison | 2015-08-11 |
| 9059285 | Structure and method for increasing strain in a device | Kevin K. Chan, Abhishek Dube | 2015-06-16 |
| 9059286 | Pre-gate, source/drain strain layer formation | Judson R. Holt, Keith H. Tabakman | 2015-06-16 |