Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10991689 | Additional spacer for self-aligned contact for only high voltage FinFETs | Abu Naser Zainuddin, Sangameshwar Rao Saudari, Wei Ma, Kai Zhao, Bala Haran | 2021-04-27 |
| 10566328 | Integrated circuit products with gate structures positioned above elevated isolation structures | Bala Haran, Mahender Kumar | 2020-02-18 |
| 10396078 | Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same | Judson R. Holt, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger +1 more | 2019-08-27 |
| 10020307 | Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same | Judson R. Holt, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger +1 more | 2018-07-10 |
| 9953873 | Methods of modulating the morphology of epitaxial semiconductor material | Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Timothy J. McArdle +1 more | 2018-04-24 |
| 9634084 | Conformal buffer layer in source and drain regions of fin-type transistors | Chengwen Pei, Eric T. Harley, Yue Ke, Henry K. Utomo, Yinxiao Yang +1 more | 2017-04-25 |
| 9287399 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt +6 more | 2016-03-15 |
| 8940595 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt +6 more | 2015-01-27 |
| 8557649 | Method for controlling structure height | Rajasekhar Venigalla, Michael V. Aquilino, Massud Aminpur, Michael P. Belyansky, Unoh Kwon +1 more | 2013-10-15 |
| 8497212 | Filling narrow openings using ion beam etch | Katherina Babich, Alessandro C. Callegari, Eugene J. O'Sullivan | 2013-07-30 |
| 7956417 | Method of reducing stacking faults through annealing | Yun-Yu Wang, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried | 2011-06-07 |
| 7911024 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Herbert L. Ho, Mahender Kumar, Qiqing C. Ouyang, Paul A. Papworth, Michael D. Steigerwalt | 2011-03-22 |
| 7893493 | Stacking fault reduction in epitaxially grown silicon | Yun-Yu Wang, Linda Black, Judson R. Holt, Woo-Hyeong Lee, Scott Luning | 2011-02-22 |
| 7871893 | Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices | Gregory Costrini, David M. Dobuzinsky, Thomas S. Kanarsky, Munir D. Naeem, Richard S. Wise | 2011-01-18 |
| 7820501 | Decoder for a stationary switch machine | Yun-Yu Wang, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried | 2010-10-26 |
| 7763518 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Herbert L. Ho, Mahender Kumar, Qiqing C. Ouyang, Paul A. Papworth, Michael D. Steigerwalt | 2010-07-27 |
| 7691716 | Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation | Herbert L. Ho, Mahender Kumar, Qiging Ouyang, Paul A. Papworth, Michael D. Steigerwalt | 2010-04-06 |
| 7674720 | Stacking fault reduction in epitaxially grown silicon | Yun-Yu Wang, Linda Black, Judson R. Holt, Woo-Hyeong Lee, Scott Luning | 2010-03-09 |
| 7498256 | Copper contact via structure using hybrid barrier layer | Randolph F. Knarr, Andrew H. Simon, Anna W. Topol, Yun-Yu Wang, Keith Kwong Hon Wong | 2009-03-03 |
| 7494918 | Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof | Byeong Y. Kim, Xiaomeng Chen, Judson R. Holt, Linda Black, Igor Peidous | 2009-02-24 |
| 7491598 | CMOS circuits including a passive element having a low end resistance | Alyssa C. Bonnoit, K. Paul Muller, Werner Rausch | 2009-02-17 |
| 7485537 | Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness | Herbert L. Ho, Mahender Kumar, Qiqing C. Ouyang, Paul A. Papworth, Michael D. Steigerwalt | 2009-02-03 |
| 7375410 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Herbert L. Ho, Mahender Kumar, Qiqing C. Ouyang, Paul A. Papworth, Michael D. Steigerwalt | 2008-05-20 |
| 7361959 | CMOS circuits including a passive element having a low end resistance | Alyssa C. Bonnoit, K. Paul Muller, Werner Rausch | 2008-04-22 |
| 7227204 | Structure for improved diode ideality | Edward P. Maciejewski, Sherry A. Womack, Shreesh Narasimha | 2007-06-05 |