PC

Paul Chang

IBM: 38 patents #2,506 of 70,183Top 4%
AS Apd Semiconductor: 10 patents #1 of 12Top 9%
Globalfoundries: 5 patents #673 of 4,424Top 20%
AD Advanced Power Devices: 4 patents #1 of 16Top 7%
SY Synopsys: 2 patents #669 of 2,302Top 30%
PL Pfc Device Holdings Limited: 2 patents #8 of 10Top 80%
DI Diodes Incorporated: 2 patents #32 of 123Top 30%
KW Kyocera Wireless: 1 patents #75 of 163Top 50%
MM Monolithic Memories: 1 patents #17 of 45Top 40%
PI P&F Brother Industrial: 1 patents #10 of 25Top 40%
TSMC: 1 patents #8,466 of 12,232Top 70%
AM American Megatrends: 1 patents #127 of 200Top 65%
BL Buffalo Machinery Company Limited: 1 patents #8 of 16Top 50%
IN Inventec: 1 patents #521 of 1,270Top 45%
Overall (All Time): #25,709 of 4,157,543Top 1%
75
Patents All Time

Issued Patents All Time

Showing 25 most recent of 75 patents

Patent #TitleCo-InventorsDate
11361140 Routing for length-matched nets in interposer designs Jitendra Kumar Gupta, Ksenia Roze, Xun Liu, Lan Luo 2022-06-14
10867106 Routing for length-matched nets in interposer designs Jitendra Kumar Gupta, Ksenia Roze, Xun Liu, Lan Luo 2020-12-15
10731705 Detecting apparatus for detecting axial displacement of bearing unit 2020-08-04
9953873 Methods of modulating the morphology of epitaxial semiconductor material Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw +1 more 2018-04-24
9941129 Semiconductor device having self-aligned gate contacts Josephine B. Chang, Michael A. Guillorn 2018-04-10
9761679 Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device Katsunori Onishi, Jian-Shen Yu 2017-09-12
9735058 Method of forming performance optimized gate structures by silicidizing lowered source and drain regions Katsunori Onishi, Jian-Shen Yu 2017-08-15
9722045 Buffer layer for modulating Vt across devices Bhupesh Chandra, Viorel Ontalus, Timothy J. McArdle, Claude Ortolland, Judson R. Holt 2017-08-01
9639652 Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors Jie Deng, Terrence B. Hook, Sim Y. Loo, Anda C. Mocuta, Jae-Eun Park +2 more 2017-05-02
9559284 Silicided nanowires for nanobridge weak links Josephine B. Chang, Guy M. Cohen, Michael A. Guillorn 2017-01-31
9484205 Semiconductor device having self-aligned gate contacts Josephine B. Chang, Michael A. Guillorn 2016-11-01
9455195 Method of forming performance optimized gate structures by silicidizing lowered source and drain regions Katsunori Onishi, Jian-Shen Yu 2016-09-27
9443951 Embedded planar source/drain stressors for a finFET including a plurality of fins Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight 2016-09-13
9406745 Method of manufacturing super junction for semiconductor device Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao 2016-08-02
9379180 Super junction for semiconductor device and method for manufacturing the same Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao 2016-06-28
9287399 Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels Bhupesh Chandra, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar +6 more 2016-03-15
9034704 6T SRAM architecture for gate-all-around nanowire devices Karthik Balakrishnan, Josephine B. Chang, Michael A. Guillorn 2015-05-19
9024355 Embedded planar source/drain stressors for a finFET including a plurality of fins Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight 2015-05-05
9000530 6T SRAM architecture for gate-all-around nanowire devices Karthik Balakrishnan, Josephine B. Chang, Michael A. Guillorn 2015-04-07
8981478 Recessed source and drain regions for FinFETs Josephine B. Chang, Michael A. Guillorn, Chung-Hsun Lin, Jeffrey W. Sleight 2015-03-17
8949080 Methods of designing integrated circuits and systems thereof Kuo-Tsai Li, Andy Chang 2015-02-03
8940595 Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels Bhupesh Chandra, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar +6 more 2015-01-27
8900959 Non-replacement gate nanomesh field effect transistor with pad regions Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight 2014-12-02
8836087 Gap-fill keyhole repair using printable dielectric material Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight 2014-09-16
8796742 Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight 2014-08-05