Issued Patents All Time
Showing 25 most recent of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12433020 | Multi-VT solution for replacement metal gate bonded stacked FET | Ruqiang Bao, Junli Wang, Heng Wu | 2025-09-30 |
| 12374615 | Electronic devices with a low dielectric constant | Hsueh-Chung Chen, Su Chen Fan, Carl Radens, Indira Seshadri | 2025-07-29 |
| 12363990 | Upper and lower gate configurations of monolithic stacked FinFET transistors | Chen Zhang, Junli Wang, Ruilong Xie, Sung-Dae Suk | 2025-07-15 |
| 12336294 | Gate-cut and separation techniques for enabling independent gate control of stacked transistors | Ruilong Xie, Nicolas Loubet, Julien Frougier, Lawrence A. Clevenger, Prasad Bhosale +2 more | 2025-06-17 |
| 12317537 | Reduced parasitic capacitance semiconductor device containing at least one local interconnect passthrough structure | Ruilong Xie, Junli Wang, Alexander Reznicek | 2025-05-27 |
| 12278237 | Stacked FETS with non-shared work function metals | Ruilong Xie, Julien Frougier, Junli Wang, Ruqiang Bao, Rishikesh Krishnan +1 more | 2025-04-15 |
| 12278184 | Vertically-stacked field effect transistor cell | Albert M. Chu, Junli Wang, Albert M. Young | 2025-04-15 |
| 12272648 | Semiconductor device having a backside power rail | Ruilong Xie, Junli Wang, Julien Frougier, Lawrence A. Clevenger | 2025-04-08 |
| 12268031 | Backside power rails and power distribution network for density scaling | Ruilong Xie, Kisik Choi, Somnath Ghosh, Sagarika Mukesh, Albert M. Chu +6 more | 2025-04-01 |
| 12176348 | Self-aligned hybrid substrate stacked gate-all-around transistors | Ruqiang Bao, Junli Wang | 2024-12-24 |
| 12176250 | Metal gate boundary for transistor scaling | Ruqiang Bao | 2024-12-24 |
| 12148833 | Three-dimensional, monolithically stacked field effect transistors formed on the front and backside of a wafer | Sung-Dae Suk, Somnath Ghosh, Chen Zhang, Junli Wang, Devendra K. Sadana | 2024-11-19 |
| 12142656 | Staggered stacked semiconductor devices | Albert M. Chu, Junli Wang, Albert M. Young, Vidhi Zalani | 2024-11-12 |
| 12107168 | Independent gate length tunability for stacked transistors | Ruqiang Bao, Junli Wang | 2024-10-01 |
| 12087691 | Semiconductor structures with backside gate contacts | Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Lawrence A. Clevenger, Nicolas Loubet +3 more | 2024-09-10 |
| 12034005 | Self-aligned metal gate with poly silicide for vertical transport field-effect transistors | Brent A. Anderson, Ruqiang Bao, Vijay Narayanan | 2024-07-09 |
| 11984401 | Stacked FET integration with BSPDN | Ruilong Xie, Junli Wang, Mukta G. Farooq | 2024-05-14 |
| 11908743 | Planar devices with consistent base dielectric | Huimei Zhou, Andrew M. Greene, Julien Frougier, Ruqiang Bao, Jingyun Zhang +1 more | 2024-02-20 |
| 11894423 | Contact resistance reduction in nanosheet device structure | Heng Wu, Ruqiang Bao, Junli Wang, Lan Yu, Reinaldo Vega +1 more | 2024-02-06 |
| 11895818 | Stacked FET SRAM | Ruilong Xie, Carl Radens, Junli Wang, Ravikumar Ramachandran, Julien Frougier | 2024-02-06 |
| 11894462 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu | 2024-02-06 |
| 11869893 | Stacked field effect transistor with wrap-around contacts | Ruilong Xie, Chun-Chen Yeh, Alexander Reznicek | 2024-01-09 |
| 11817501 | Three-dimensional, monolithically stacked field effect transistors formed on the front and backside of a wafer | Sung-Dae Suk, Somnath Ghosh, Chen Zhang, Junli Wang, Devendra K. Sadana | 2023-11-14 |
| 11757012 | Source and drain contact cut last process to enable wrap-around-contact | Andrew M. Greene, Tenko Yamashita, Veeraraghavan S. Basker, Robert R. Robison, Ardasheir Rahman | 2023-09-12 |
| 11749744 | Fin structure for vertical transport field effect transistor | Heng Wu, Lan Yu, Junli Wang, Ruqiang Bao, Ruilong Xie | 2023-09-05 |