Issued Patents All Time
Showing 51–75 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10797163 | Leakage control for gate-all-around field-effect transistor devices | Lan Yu, Heng Wu, Ruqiang Bao, Junli Wang | 2020-10-06 |
| 10692778 | Gate-all-around FETs having uniform threshold voltage | Ruqiang Bao, Junli Wang, Heng Wu | 2020-06-23 |
| 10685866 | Fin isolation to mitigate local layout effects | Huimei Zhou, Gen Tsutsui, Andrew M. Greene, Huiming Bu, Robert R. Robison +2 more | 2020-06-16 |
| 10664966 | Anomaly detection using image-based physical characterization | Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou | 2020-05-26 |
| 10658224 | Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects | Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Andrew M. Greene, Huiming Bu +1 more | 2020-05-19 |
| 10593802 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu | 2020-03-17 |
| 10586700 | Protection of low temperature isolation fill | Michael P. Belyansky, Richard A. Conti, Devendra K. Sadana, Jay William Strane | 2020-03-10 |
| 10573646 | Preserving channel strain in fin cuts | Andrew M. Greene, Ravikumar Ramachandran, Rajasekhar Venigalla | 2020-02-25 |
| 10535517 | Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS | Choonghyun Lee, Ruqiang Bao, Gen Tsutsui | 2020-01-14 |
| 10535773 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh | 2020-01-14 |
| 10535550 | Protection of low temperature isolation fill | Michael P. Belyansky, Richard A. Conti, Devendra K. Sadana, Jay William Strane | 2020-01-14 |
| 10510892 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu | 2019-12-17 |
| 10468412 | Formation of a semiconductor device with selective nitride grown on conductor | Ruqiang Bao, Zuoguang Liu | 2019-11-05 |
| 10381479 | Interface charge reduction for SiGe surface | Devendra K. Sadana, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki +3 more | 2019-08-13 |
| 10361210 | Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh | 2019-07-23 |
| 10355106 | Replacement metal gate scheme with self-alignment gate for vertical field effect transistors | Raqiang Bao | 2019-07-16 |
| 10332883 | Integrated metal gate CMOS devices | Ruqiang Bao, Vijay Narayanan | 2019-06-25 |
| 10312370 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu | 2019-06-04 |
| 10263098 | Threshold voltage modulation through channel length adjustment | Ruqiang Bao, Derrick Liu, Huimei Zhou | 2019-04-16 |
| 10256238 | Preserving channel strain in fin cuts | Andrew M. Greene, Ravikumar Ramachandran, Rajasekhar Venigalla | 2019-04-09 |
| 10256150 | Fabricating Fin-based split-gate high-drain-voltage transistor by work function tuning | Liyang Song, Xinhui Wang, Qintao Zhang | 2019-04-09 |
| 10249714 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction | Shogo Mochizuki, Andreas Scholze, Chun-Chen Yeh | 2019-04-02 |
| 10249542 | Self-aligned doping in source/drain regions for low contact resistance | Zuoguang Liu, Gen Tsutsui, Heng Wu | 2019-04-02 |
| 10249758 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh | 2019-04-02 |
| 10224419 | Threshold voltage modulation through channel length adjustment | Ruqiang Bao, Derrick Liu, Huimei Zhou | 2019-03-05 |