Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12402352 | Unipolar-FET implementation in stacked-FET CMOS | Shogo Mochizuki | 2025-08-26 |
| 12119264 | Non-step nanosheet structure for stacked field-effect transistors | Shogo Mochizuki | 2024-10-15 |
| 11830946 | Bottom source/drain for fin field effect transistors | Heng Wu, Shogo Mochizuki, Kangguo Cheng | 2023-11-28 |
| 11616140 | Vertical transport field effect transistor with bottom source/drain | Heng Wu, Lan Yu, Ruilong Xie | 2023-03-28 |
| 11282962 | Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT) | Huimei Zhou, Ruqiang Bao, Michael P. Belyansky, Andrew M. Greene | 2022-03-22 |
| 11276781 | Bottom source/drain for fin field effect transistors | Heng Wu, Shogo Mochizuki, Kangguo Cheng | 2022-03-15 |
| 11183427 | Differing device characteristics on a single wafer by selective etch | Huimei Zhou, Shogo Mochizuki, Ruqiang Bao | 2021-11-23 |
| 11056588 | Vertical transport field effect transistor with bottom source/drain | Heng Wu, Lan Yu, Ruilong Xie | 2021-07-06 |
| 11037905 | Formation of stacked vertical transport field effect transistors | Heng Wu, Tenko Yamashita | 2021-06-15 |
| 10971626 | Interface charge reduction for SiGe surface | Devendra K. Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell +3 more | 2021-04-06 |
| 10957646 | Hybrid BEOL metallization utilizing selective reflection mask | Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Ruqiang Bao +2 more | 2021-03-23 |
| 10937648 | Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS | Choonghyun Lee, Ruqiang Bao, Dechao Guo | 2021-03-02 |
| 10892181 | Semiconductor device with mitigated local layout effects | Huimei Zhou, Veeraraghavan S. Basker, Andrew M. Greene, Dechao Guo, Huiming Bu +1 more | 2021-01-12 |
| 10685866 | Fin isolation to mitigate local layout effects | Huimei Zhou, Andrew M. Greene, Dechao Guo, Huiming Bu, Robert R. Robison +2 more | 2020-06-16 |
| 10679901 | Differing device characteristics on a single wafer by selective etch | Huimei Zhou, Shogo Mochizuki, Ruqiang Bao | 2020-06-09 |
| 10672910 | Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT) | Huimei Zhou, Ruqiang Bao, Michael P. Belyansky, Andrew M. Greene | 2020-06-02 |
| 10658224 | Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects | Huimei Zhou, Veeraraghavan S. Basker, Andrew M. Greene, Dechao Guo, Huiming Bu +1 more | 2020-05-19 |
| 10586767 | Hybrid BEOL metallization utilizing selective reflection mask | Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Ruqiang Bao +2 more | 2020-03-10 |
| 10535773 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Chun-Chen Yeh | 2020-01-14 |
| 10535517 | Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS | Choonghyun Lee, Ruqiang Bao, Dechao Guo | 2020-01-14 |
| 10381479 | Interface charge reduction for SiGe surface | Devendra K. Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell +3 more | 2019-08-13 |
| 10319811 | Semiconductor device including fin having condensed channel region | Hong He, Effendi Leobandung, Tenko Yamashita | 2019-06-11 |
| 10312245 | Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared pFET and nFET trench | Zuoguang Liu, Heng Wu, Peng Xu | 2019-06-04 |
| 10249542 | Self-aligned doping in source/drain regions for low contact resistance | Dechao Guo, Zuoguang Liu, Heng Wu | 2019-04-02 |
| 10249758 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Chun-Chen Yeh | 2019-04-02 |