Issued Patents All Time
Showing 25 most recent of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12272545 | Embedded metal contamination removal from BEOL wafers | Devika Sil, Ashim Dutta, Yann Mignot, John C. Arnold, Daniel C. Edelstein +1 more | 2025-04-08 |
| 12266607 | Bottom barrier free interconnects without voids | Kenneth Chun Kuen Cheng, Koichi Motoyama, Kisik Choi, Hosadurga Shobha, Joe Lee | 2025-04-01 |
| 11804378 | Surface conversion in chemical mechanical polishing | Raghuveer R. Patlolla, Donald F. Canaperi, Chih-Chao Yang, Mary Breton | 2023-10-31 |
| 11637036 | Planarization stop region for use with low pattern density interconnects | Hari Prasad Amanapu, Raghuveer R. Patlolla, Koichi Motoyama, Chih-Chao Yang | 2023-04-25 |
| 11404311 | Metallic interconnect structures with wrap around capping layers | Kedari Matam, Chih-Chao Yang, Theo Standaert | 2022-08-02 |
| 11322361 | Selective etching of silicon wafer | Da Song, Allan Upham, Kevin R. Winstel, Spyridon Skordas | 2022-05-03 |
| 11315830 | Metallic interconnect structures with wrap around capping layers | Kedari Matam, Chih-Chao Yang, Theo Standaert | 2022-04-26 |
| 11276636 | Adjustable via dimension and chamfer angle | Lawrence A. Clevenger, Koichi Motoyama, Gangadhara Raja Muthinti, Benjamin D. Briggs, Michael Rizzolo | 2022-03-15 |
| 11251126 | Replacement metal cap by an exchange reaction | James J. Kelly | 2022-02-15 |
| 11244859 | Interconnects having a via-to-line spacer for preventing short circuit events between a conductive via and an adjacent line | Koichi Motoyama, Christopher J. Penny, Nicholas Anthony Lanzillo, Lawrence A. Clevenger | 2022-02-08 |
| 11205587 | Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability | Su Chen Fan, Hemanth Jagannathan, Raghuveer R. Patlolla | 2021-12-21 |
| 11171001 | Multiple patterning scheme integration with planarized cut patterning | Hsueh-Chung Chen, Yongan Xu, Lawrence A. Clevenger, Yann Mignot | 2021-11-09 |
| 11171054 | Selective deposition with SAM for fully aligned via | Son V. Nguyen, Rudy J. Wojtecki, Noel Arellano, Alexander Edward Hess, Thomas J. Haigh, Jr. +1 more | 2021-11-09 |
| 11164878 | Interconnect and memory structures having reduced topography variation formed in the BEOL | Chih-Chao Yang, Baozhen Li, Raghuveer R. Patlolla | 2021-11-02 |
| 11164776 | Metallic interconnect structure | Son V. Nguyen, Takeshi Nogami, Thomas J. Haigh, Jr., Matthew T. Shoudy | 2021-11-02 |
| 11164815 | Bottom barrier free interconnects without voids | Kenneth Chun Kuen Cheng, Koichi Motoyama, Kisik Choi, Hosadurga Shobha, Joe Lee | 2021-11-02 |
| 11101172 | Dielectric damage-free dual damascene Cu interconnects without barrier at via bottom | Koichi Motoyama, Benjamin D. Briggs, Gangadhara Raja Muthinti, Lawrence A. Clevenger | 2021-08-24 |
| 11094527 | Wet clean solutions to prevent pattern collapse | Chih-Chao Yang, Raghuveer R. Patlolla, Hsueh-Chung Chen | 2021-08-17 |
| 11037795 | Planarization of dielectric topography and stopping in dielectric | Hari Prasad Amanapu, Iqbal Rashid Saraf, Raghuveer R. Patlolla, Chih-Chao Yang | 2021-06-15 |
| 11031339 | Metal interconnects | Raghuveer R. Patlolla, Chih-Chao Yang | 2021-06-08 |
| 11018087 | Metal interconnects | Raghuveer R. Patlolla, Chih-Chao Yang | 2021-05-25 |
| 11004735 | Conductive interconnect having a semi-liner and no top surface recess | Michael Rizzolo, Oscar van der Straten, Chih-Chao Yang | 2021-05-11 |
| 10978388 | Skip via for metal interconnects | Hari Prasad Amanapu, Prasad Bhosale, Nicholas V. LiCausi, Lars Liebmann, James Jay McMahon +1 more | 2021-04-13 |
| 10957646 | Hybrid BEOL metallization utilizing selective reflection mask | Benjamin D. Briggs, Michael Rizzolo, Koichi Motoyama, Gen Tsutsui, Ruqiang Bao +2 more | 2021-03-23 |
| 10937653 | Multiple patterning scheme integration with planarized cut patterning | Hsueh-Chung Chen, Yongan Xu, Lawrence A. Clevenger, Yann Mignot | 2021-03-02 |