Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12107008 | Maskless alignment scheme for BEOL memory array manufacturing | Soon-Cheon Seo, Dexin Kong, Muthumanickam Sankarapandian | 2024-10-01 |
| 12087685 | Semiconductor interconnect structure with double conductors | Benjamin D. Briggs, Takeshi Nogami | 2024-09-10 |
| 11804378 | Surface conversion in chemical mechanical polishing | Donald F. Canaperi, Cornelius Brown Peethala, Chih-Chao Yang, Mary Breton | 2023-10-31 |
| 11664271 | Dual damascene with short liner | Koichi Motoyama, Oscar van der Straten, Joseph F. Maniscalco, Alexander Reznicek, Theodorus E. Standaert | 2023-05-30 |
| 11637036 | Planarization stop region for use with low pattern density interconnects | Cornelius Brown Peethala, Hari Prasad Amanapu, Koichi Motoyama, Chih-Chao Yang | 2023-04-25 |
| 11205587 | Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability | Su Chen Fan, Hemanth Jagannathan, Cornelius Brown Peethala | 2021-12-21 |
| 11164878 | Interconnect and memory structures having reduced topography variation formed in the BEOL | Chih-Chao Yang, Baozhen Li, Cornelius Brown Peethala | 2021-11-02 |
| 11133457 | Controllable formation of recessed bottom electrode contact in a memory metallization stack | James J. Kelly, Chih-Chao Yang | 2021-09-28 |
| 11094527 | Wet clean solutions to prevent pattern collapse | Cornelius Brown Peethala, Chih-Chao Yang, Hsueh-Chung Chen | 2021-08-17 |
| 11037875 | Forming dual metallization interconnect structures in single metallization level | Hari Prasad Amanapu, Charan V. Surisetty | 2021-06-15 |
| 11037795 | Planarization of dielectric topography and stopping in dielectric | Hari Prasad Amanapu, Cornelius Brown Peethala, Iqbal Rashid Saraf, Chih-Chao Yang | 2021-06-15 |
| 11031337 | Forming dual metallization interconnect structures in single metallization level | Hari Prasad Amanapu, Charan V. Surisetty | 2021-06-08 |
| 11031250 | Semiconductor structures of more uniform thickness | Mona A. Ebrish, Michael Rizzolo, Son V. Nguyen, Donald F. Canaperi | 2021-06-08 |
| 11031339 | Metal interconnects | Cornelius Brown Peethala, Chih-Chao Yang | 2021-06-08 |
| 11018087 | Metal interconnects | Cornelius Brown Peethala, Chih-Chao Yang | 2021-05-25 |
| 10916431 | Robust gate cap for protecting a gate from downstream metallization etch operations | Hari Prasad Amanapu, Vimal Kamineni, Sugirtha Krishnamurthy, Viraj Y. Sardesai, Cornelius Brown Peethala | 2021-02-09 |
| 10910307 | Back end of line metallization structure | James J. Kelly, Cornelius Brown Peethala, Chih-Chao Yang | 2021-02-02 |
| 10903161 | Back end of line metallization structure | James J. Kelly, Cornelius Brown Peethala, Chih-Chao Yang | 2021-01-26 |
| 10896846 | Controlling performance and reliability of conductive regions in a metallization network | Cornelius Brown Peethala, Chih-Chao Yang | 2021-01-19 |
| 10833122 | Bottom electrode and dielectric structure for MRAM applications | Hari Prasad Amanapu, Cornelius Brown Peethala, Michael Rizzolo | 2020-11-10 |
| 10832917 | Low oxygen cleaning for CMP equipment | Donald F. Canaperi, Pavan S. Chinthamanipeta, Cornelius Brown Peethala | 2020-11-10 |
| 10804193 | Semiconductor interconnect structure with double conductors | Benjamin D. Briggs, Takeshi Nogami | 2020-10-13 |
| 10741748 | Back end of line metallization structures | Joseph F. Maniscalco, Cornelius Brown Peethala, Chih-Chao Yang | 2020-08-11 |
| 10714382 | Controlling performance and reliability of conductive regions in a metallization network | Cornelius Brown Peethala, Chih-Chao Yang | 2020-07-14 |
| 10699945 | Back end of line integration for interconnects | Cornelius Brown Peethala, Chih-Chao Yang, Roger A. Quon | 2020-06-30 |