Issued Patents All Time
Showing 25 most recent of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12297884 | Impact absorbing apparatus | — | 2025-05-13 |
| 11948442 | Device and system for ultrasonic transmission of accelerometer data | Patrick LaFontaine | 2024-04-02 |
| 11848273 | Bridge chip with through via | Mukta G. Farooq | 2023-12-19 |
| 11784120 | Metal via structure | Yann Mignot, Muthumanickam Sankarapandian, Yongan Xu, Hsueh-Chung Chen, Daniel J. Vincent | 2023-10-10 |
| 11682640 | Protective surface layer on under bump metallurgy for solder joining | Mukta G. Farooq | 2023-06-20 |
| 11341831 | Device and system for ultrasonic transmission of accelerometer data | Patrick LaFontaine | 2022-05-24 |
| 11315831 | Dual redistribution layer structure | Mukta G. Farooq | 2022-04-26 |
| 11282716 | Integration structure and planar joining | Mukta G. Farooq | 2022-03-22 |
| 11264306 | Hybrid TIMs for electronic package cooling | Kamal K. Sikka, Piyas Bal Chowdhury, Jeffrey A. Zitz, Sushumna Iruvanti, Shidong Li | 2022-03-01 |
| 11251126 | Replacement metal cap by an exchange reaction | Cornelius Brown Peethala | 2022-02-15 |
| 11239167 | Cu—Cu bonding for interconnects on bridge chip attached to chips and packaging substrate | Mukta G. Farooq, Ravi K. Bonam, Spyridon Skordas | 2022-02-01 |
| 11171006 | Simultaneous plating of varying size features on semiconductor substrate | Mukta G. Farooq | 2021-11-09 |
| 11152298 | Metal via structure | Yann Mignot, Muthumanickam Sankarapandian, Yongan Xu, Hsueh-Chung Chen, Daniel J. Vincent | 2021-10-19 |
| 11133457 | Controllable formation of recessed bottom electrode contact in a memory metallization stack | Raghuveer R. Patlolla, Chih-Chao Yang | 2021-09-28 |
| 11069564 | Double metal patterning | Hsueh-Chung Chen, Yongan Xu, Yann Mignot, Lawrence A. Clevenger | 2021-07-20 |
| 11063126 | Metal contact isolation for semiconductor structures | Su Chen Fan, Yann Mignot, Hsueh-Chung Chen | 2021-07-13 |
| 11049844 | Semiconductor wafer having trenches with varied dimensions for multi-chip modules | Ravi K. Bonam, Mukta G. Farooq, Dinesh Gupta, Kamal K. Sikka, Joshua M. Rubin | 2021-06-29 |
| 10978342 | Interconnect with self-forming wrap-all-around barrier layer | Huai Huang, Takeshi Nogami, Alfred Grill, Benjamin D. Briggs, Nicholas Anthony Lanzillo +3 more | 2021-04-13 |
| 10971356 | Stack viabar structures | Su Chen Fan, Hsueh-Chung Chen, Yann Mignot, Terence B. Hook | 2021-04-06 |
| 10943883 | Planar wafer level fan-out of multi-chip modules having different size chips | Ravi K. Bonam, Mukta G. Farooq, Dinesh Gupta | 2021-03-09 |
| 10910307 | Back end of line metallization structure | Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang | 2021-02-02 |
| 10903161 | Back end of line metallization structure | Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang | 2021-01-26 |
| 10903116 | Void-free metallic interconnect structures with self-formed diffusion barrier layers | Joseph F. Maniscalco, Koichi Motoyama, Hosadurga Shobha, Chih-Chao Yang | 2021-01-26 |
| 10832973 | Stress modulation of nFET and pFET fin structures | Huimei Zhou, Kangguo Cheng, Michael P. Belyansky, Oleg Gluschenkov, Richard A. Conti +1 more | 2020-11-10 |
| 10825726 | Metal spacer self aligned multi-patterning integration | Hsueh-Chung Chen, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger | 2020-11-03 |