Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11569442 | Dielectric retention and method of forming memory pillar | Saba Zare, Michael Rizzolo, Theodorus E. Standaert | 2023-01-31 |
| 11043494 | Structure and method for equal substrate to channel height between N and P fin-FETs | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie, Deepika Priyadarshini +2 more | 2021-06-22 |
| 11031250 | Semiconductor structures of more uniform thickness | Michael Rizzolo, Son V. Nguyen, Raghuveer R. Patlolla, Donald F. Canaperi | 2021-06-08 |
| 10818751 | Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions | Fee Li Lie, Nicolas Loubet, Gauri Karve, Indira Seshadri, Lawrence A. Clevenger +1 more | 2020-10-27 |
| 10811528 | Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs | Xuefeng Liu, Brent A. Anderson, Huiming Bu, Junli Wang | 2020-10-20 |
| 10804106 | High temperature ultra-fast annealed soft mask for semiconductor devices | Oleg Gluschenkov, Indira Seshadri, Ekmini Anuja De Silva | 2020-10-13 |
| 10734523 | Nanosheet substrate to source/drain isolation | Fee Li Lie, Ekmini Anuja De Silva, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger +2 more | 2020-08-04 |
| 10388789 | Reducing series resistance between source and/or drain regions and a channel region | Oleg Gluschenkov | 2019-08-20 |
| 10381348 | Structure and method for equal substrate to channel height between N and P fin-FETs | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie, Deepika Priyadarshini +2 more | 2019-08-13 |
| 10361127 | Vertical transport FET with two or more gate lengths | Gauri Karve, Fee Li Lie, Indira Seshadri, Leigh Anne H. Clevenger, Ekmini Anuja De Silva +1 more | 2019-07-23 |
| 10361306 | High acceptor level doping in silicon germanium | Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek | 2019-07-23 |
| 10319855 | Reducing series resistance between source and/or drain regions and a channel region | Oleg Gluschenkov | 2019-06-11 |
| 10229910 | Separate N and P fin etching for reduced CMOS device leakage | Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie +3 more | 2019-03-12 |
| 9799736 | High acceptor level doping in silicon germanium | Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek | 2017-10-24 |
| 9711507 | Separate N and P fin etching for reduced CMOS device leakage | Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie +3 more | 2017-07-18 |
| 9666486 | Contained punch through stopper for CMOS structures on a strain relaxed buffer substrate | Hemanth Jagannathan, Shogo Mochizuki, Alexander Reznicek | 2017-05-30 |