Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Mona A. Ebrish — 18 Patents

IBM: 16 patents #6,980 of 70,183Top 10%
Albany, NY: #100 of 790 inventorsTop 15%
New York: #7,989 of 115,490 inventorsTop 7%
Overall (All Time): #245,716 of 4,157,543Top 6%
18 Patents All Time
Mona A. Ebrish has been granted 18 US patents while listed as an inventor at IBM. The first was granted in 2017 and the most recent in November 2025. Mona A. Ebrish ranks #245,716 of 4,157,543 US inventors in our database (top 5.9%). Patent records list Mona A. Ebrish in Albany, NY, US.

Issued Patents All Time

Showing 1–18 of 18 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12476111 Selective area diffusion doping of III-N materials Travis J. Anderson, Alan G. Jacobs, Karl D. Hobart, Francis J. Kub 2025-11-18
12439653 Multi-layer hybrid edge termination for III-N power devices Travis J. Anderson, Andrew D. Koehler, Alan G. Jacobs, Matthew A. Porter, Karl D. Hobart +5 more 2025-10-07
11569442 Dielectric retention and method of forming memory pillar Saba Zare, Michael Rizzolo, Theodorus E. Standaert 2023-01-31 $7,725,000
11043494 Structure and method for equal substrate to channel height between N and P fin-FETs Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie, Deepika Priyadarshini +2 more 2021-06-22 $6,016,000
11031250 Semiconductor structures of more uniform thickness Michael Rizzolo, Son V. Nguyen, Raghuveer R. Patlolla, Donald F. Canaperi 2021-06-08 $4,452,000
10818751 Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions Fee Li Lie, Nicolas Loubet, Gauri Karve, Indira Seshadri, Lawrence A. Clevenger +1 more 2020-10-27 $6,165,000
10811528 Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs Xuefeng Liu, Brent A. Anderson, Huiming Bu, Junli Wang 2020-10-20 $3,651,000
10804106 High temperature ultra-fast annealed soft mask for semiconductor devices Oleg Gluschenkov, Indira Seshadri, Ekmini Anuja De Silva 2020-10-13 $4,674,000
10734523 Nanosheet substrate to source/drain isolation Fee Li Lie, Ekmini Anuja De Silva, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger +2 more 2020-08-04 $3,150,000
10388789 Reducing series resistance between source and/or drain regions and a channel region Oleg Gluschenkov 2019-08-20 $1,949,000
10381348 Structure and method for equal substrate to channel height between N and P fin-FETs Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie, Deepika Priyadarshini +2 more 2019-08-13 $1,909,000
10361127 Vertical transport FET with two or more gate lengths Gauri Karve, Fee Li Lie, Indira Seshadri, Leigh Anne H. Clevenger, Ekmini Anuja De Silva +1 more 2019-07-23 $2,519,000
10361306 High acceptor level doping in silicon germanium Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek 2019-07-23 $2,519,000
10319855 Reducing series resistance between source and/or drain regions and a channel region Oleg Gluschenkov 2019-06-11 $1,829,000
10229910 Separate N and P fin etching for reduced CMOS device leakage Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie +3 more 2019-03-12 $2,141,000
9799736 High acceptor level doping in silicon germanium Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek 2017-10-24 $3,030,000
9711507 Separate N and P fin etching for reduced CMOS device leakage Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie +3 more 2017-07-18 $2,009,000
9666486 Contained punch through stopper for CMOS structures on a strain relaxed buffer substrate Hemanth Jagannathan, Shogo Mochizuki, Alexander Reznicek 2017-05-30 $1,983,000