Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10957850 | Multi-layer encapsulation to enable endpoint-based process control for embedded memory fabrication | Ashim Dutta, Son V. Nguyen, Michael Rizzolo, John C. Arnold | 2021-03-23 |
| 10832945 | Techniques to improve critical dimension width and depth uniformity between features with different layout densities | Nicole Saulnier, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve +3 more | 2020-11-10 |
| 10714683 | Multilayer hardmask for high performance MRAM devices | Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, John C. Arnold | 2020-07-14 |
| 10692925 | Dielectric fill for memory pillar elements | Michael Rizzolo, Theodorus E. Standaert, Chih-Chao Yang, Son V. Nguyen | 2020-06-23 |
| 10680169 | Multilayer hardmask for high performance MRAM devices | Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, John C. Arnold | 2020-06-09 |
| 10672618 | Systems and methods for patterning features in tantalum nitride (TaN) layer | Vinh Luong, Ashim Dutta | 2020-06-02 |
| 10622250 | Dielectric gap fill evaluation for integrated circuits | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Ekmini Anuja De Silva, Gauri Karve, Fee Li Lie +3 more | 2020-04-14 |
| 10312140 | Dielectric gap fill evaluation for integrated circuits | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Ekmini Anuja De Silva, Gauri Karve, Fee Li Lie +3 more | 2019-06-04 |
| 10229910 | Separate N and P fin etching for reduced CMOS device leakage | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve, Fee Li Lie +3 more | 2019-03-12 |
| 9711507 | Separate N and P fin etching for reduced CMOS device leakage | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve, Fee Li Lie +3 more | 2017-07-18 |