Issued Patents All Time
Showing 25 most recent of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12272545 | Embedded metal contamination removal from BEOL wafers | Devika Sil, Ashim Dutta, Yann Mignot, Daniel C. Edelstein, Kedari Matam +1 more | 2025-04-08 |
| 12268031 | Backside power rails and power distribution network for density scaling | Ruilong Xie, Kisik Choi, Somnath Ghosh, Sagarika Mukesh, Albert M. Chu +6 more | 2025-04-01 |
| 12243771 | Selective patterning of vias with hardmasks | Ashim Dutta, Dominik Metzler, Timothy Mathew Philip, Sagarika Mukesh | 2025-03-04 |
| 12020949 | Subtractive patterning of interconnect structures | Dominik Metzler, Somnath Ghosh, Ekmini Anuja De Silva | 2024-06-25 |
| 11830807 | Placing top vias at line ends by selective growth of via mask from line cut dielectric | Ashim Dutta, Ekmini Anuja De Silva, Dominik Metzler | 2023-11-28 |
| 11688636 | Spin on scaffold film for forming topvia | Somnath Ghosh, Karen E. Petrillo, Cody J. Murray, Ekmini Anuja De Silva, Chi-Chun Liu +1 more | 2023-06-27 |
| 11462583 | Embedding magneto-resistive random-access memory devices between metal levels | Ashim Dutta, Chih-Chao Yang, Daniel C. Edelstein, Theodorus E. Standaert | 2022-10-04 |
| 11404317 | Method for fabricating a semiconductor device including self-aligned top via formation at line ends | Ashim Dutta, Dominik Metzler, Ekmini Anuja De Silva | 2022-08-02 |
| 11302533 | Selective gas etching for self-aligned pattern transfer | Sean D. Burns, Yann Mignot, Yongan Xu | 2022-04-12 |
| 11276607 | Selective patterning of vias with hardmasks | Ashim Dutta, Dominik Metzler, Timothy Mathew Philip, Sagarika Mukesh | 2022-03-15 |
| 11239077 | Litho-etch-litho-etch with self-aligned blocks | Chi-Chun Liu, Nelson Felix, Yann Mignot, Ekmini Anuja De Silva, Allen H. Gabor | 2022-02-01 |
| 11195995 | Back-end-of-line compatible processing for forming an array of pillars | Chi-Chun Liu, Yann Mignot, Ekmini Anuja De Silva, Nelson Felix | 2021-12-07 |
| 11189527 | Self-aligned top vias over metal lines formed by a damascene process | Timothy Mathew Philip, Sagarika Mukesh, Dominik Metzler, Ashim Dutta | 2021-11-30 |
| 11189783 | Embedded MRAM device formation with self-aligned dielectric cap | Dominik Metzler, Ashim Dutta, Donald F. Canaperi | 2021-11-30 |
| 11189561 | Placing top vias at line ends by selective growth of via mask from line cut dielectric | Ashim Dutta, Ekmini Anuja De Silva, Dominik Metzler | 2021-11-30 |
| 11189528 | Subtractive RIE interconnect | Balasubramanian S. Pranatharthi Haran, Takeshi Nogami | 2021-11-30 |
| 11171002 | Alternating hardmasks for tight-pitch line formation | Anuja E. DeSilva, Nelson Felix, Chi-Chun Liu, Yann Mignot, Stuart A. Sieg | 2021-11-09 |
| 11158786 | MRAM device formation with controlled ion beam etch of MTJ | Ashim Dutta, Chih-Chao Yang, Lijuan Zou | 2021-10-26 |
| 11152261 | Self-aligned top via formation at line ends | Ashim Dutta, Dominik Metzler | 2021-10-19 |
| 11133260 | Self-aligned top via | Chi-Chun Liu, Dominik Metzler, Nelson Felix, Ashim Dutta | 2021-09-28 |
| 10957850 | Multi-layer encapsulation to enable endpoint-based process control for embedded memory fabrication | Ashim Dutta, Isabel Cristina Chu, Son V. Nguyen, Michael Rizzolo | 2021-03-23 |
| 10930504 | Selective gas etching for self-aligned pattern transfer | Sean D. Burns, Yann Mignot, Yongan Xu | 2021-02-23 |
| 10879068 | Extreme ultraviolet lithography for high volume manufacture of a semiconductor device | Yongan Xu, Yann Mignot, Oleg Gluschenkov | 2020-12-29 |
| 10833257 | Formation of embedded magnetic random-access memory devices with multi-level bottom electrode via contacts | Ashim Dutta, Chih-Chao Yang, Theodorus E. Standaert | 2020-11-10 |
| 10833258 | MRAM device formation with in-situ encapsulation | Ashim Dutta, Chih-Chao Yang, Daniel C. Edelstein, Karthik Yogendra | 2020-11-10 |