Issued Patents All Time
Showing 25 most recent of 142 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426320 | Vertically stacked fin semiconductor devices | Praveen Joseph, Tao Li, Indira Seshadri | 2025-09-23 |
| 12363913 | Fabrication of embedded memory devices utilizing a self assembled monolayer | Ashim Dutta, Chih-Chao Yang | 2025-07-15 |
| 12310100 | Dielectric reflow for boundary control | Jing Guo, Nicolas Loubet, Indira Seshadri, Ruqiang Bao, Nelson Felix | 2025-05-20 |
| 12183630 | Additive interconnect formation | Ashim Dutta, Chih-Chao Yang, Jennifer Church | 2024-12-31 |
| 12125790 | Airgap isolation for back-end-of-the-line semiconductor interconnect structure with top via | Ashim Dutta, Praveen Joseph, Jennifer Church | 2024-10-22 |
| 12033856 | Litho-litho-etch (LLE) multi color resist | Yann Mignot, Dario L. Goldfarb | 2024-07-09 |
| 12020949 | Subtractive patterning of interconnect structures | Dominik Metzler, Somnath Ghosh, John C. Arnold | 2024-06-25 |
| 12019376 | Polymer brush adhesion promoter with UV cleavable linker | Jing Guo, Bharat Kumar, Jennifer Church, Dario L. Goldfarb, Nelson Felix | 2024-06-25 |
| 12002856 | Vertical field effect transistor with crosslink fin arrangement | Indira Seshadri, Ruilong Xie, Chen Zhang | 2024-06-04 |
| 11990342 | Metal cut patterning and etching to minimize interlayer dielectric layer loss | Kisup Chung, Andrew M. Greene, Siva Kanakasabapathy, Indira Seshadri | 2024-05-21 |
| 11935931 | Selective shrink for contact trench | Ruilong Xie, Jing Guo, Abraham Arceo de la Pena | 2024-03-19 |
| 11923311 | Forming self-aligned multi-metal interconnects | Ashim Dutta | 2024-03-05 |
| 11923246 | Via CD controllable top via structure | Koichi Motoyama, Dominik Metzler, Chanro Park, Hsueh-Chung Chen | 2024-03-05 |
| 11916143 | Vertical transport field-effect transistor with gate patterning | Ruilong Xie, Wenyu Xu, Indira Seshadri, Jing Guo | 2024-02-27 |
| 11906901 | Alternating copolymer chain scission photoresists | Dario L. Goldfarb, Jing Guo, Jennifer Church, Luciana Meli | 2024-02-20 |
| 11856878 | High-density resistive random-access memory array with self-aligned bottom electrode contact | Dexin Kong, Ashim Dutta, Daniel Schmidt | 2023-12-26 |
| 11830807 | Placing top vias at line ends by selective growth of via mask from line cut dielectric | Ashim Dutta, Dominik Metzler, John C. Arnold | 2023-11-28 |
| 11810828 | Transistor boundary protection using reversible crosslinking reflow | Jing Guo, Indira Seshadri, Jingyun Zhang, Su Chen Fan | 2023-11-07 |
| 11804401 | Spacer-defined process for lithography-etch double patterning for interconnects | Nelson Felix, Luciana Meli Thompson, Yann Mignot | 2023-10-31 |
| 11778929 | Selective encapsulation for metal electrodes of embedded memory devices | Ashim Dutta, Jennifer Church | 2023-10-03 |
| 11756961 | Staggered stacked vertical crystalline semiconducting channels | Tsung-Sheng Kang, Tao Li, Ardasheir Rahman, Praveen Joseph, Indira Seshadri | 2023-09-12 |
| 11751492 | Embedded memory pillar | Dexin Kong, Ashim Dutta, Daniel Schmidt | 2023-09-05 |
| 11744083 | Fabrication of embedded memory devices utilizing a self assembled monolayer | Ashim Dutta, Chih-Chao Yang | 2023-08-29 |
| 11699592 | Inverse tone pillar printing method using organic planarizing layer pillars | Nelson Felix, Praveen Joseph, Ashim Dutta | 2023-07-11 |
| 11688636 | Spin on scaffold film for forming topvia | Somnath Ghosh, Karen E. Petrillo, Cody J. Murray, Chi-Chun Liu, Dominik Metzler +1 more | 2023-06-27 |