Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12396212 | Gate all-around device with through-stack nanosheet 2D channel | Tao Li, Ardasheir Rahman, Shogo Mochizuki | 2025-08-19 |
| 12324237 | Diffusion-break region in stacked-FET integrated circuit device | Ruilong Xie, Alexander Reznicek, Daniel Schmidt | 2025-06-03 |
| 12310102 | Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers | Ardasheir Rahman, Tao Li, Su Chen Fan | 2025-05-20 |
| 12266605 | Top via interconnects with line wiggling prevention | Tao Li, Ruilong Xie, Chih-Chao Yang | 2025-04-01 |
| 12262552 | Source/drain epitaxy process in stacked FET | Daniel Schmidt, Alexander Reznicek, Ruilong Xie | 2025-03-25 |
| 12080640 | Self-aligned via to metal line for interconnect | Tao Li, Ruilong Xie, Alexander Reznicek | 2024-09-03 |
| 12075627 | AI accelerator with MRAM, PCM, and recessed PCM bottom electrode | Ruilong Xie, Alexander Reznicek, Wei Wang, Tao Li | 2024-08-27 |
| 11956939 | Static random access memory using vertical transport field effect transistors | Ardasheir Rahman, Tao Li, Albert M. Young | 2024-04-09 |
| 11942424 | Via patterning for integrated circuits | Tao Li, Ruilong Xie, Chih-Chao Yang | 2024-03-26 |
| 11849647 | Nonmetallic liner around a magnetic tunnel junction | Tao Li, Yann Mignot, Ashim Dutta, Wenyu Xu | 2023-12-19 |
| 11810918 | Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers | Ardasheir Rahman, Tao Li, Su Chen Fan | 2023-11-07 |
| 11756961 | Staggered stacked vertical crystalline semiconducting channels | Tao Li, Ardasheir Rahman, Praveen Joseph, Indira Seshadri, Ekmini Anuja De Silva | 2023-09-12 |
| 11678475 | Static random access memory using vertical transport field effect transistors | Ardasheir Rahman, Tao Li, Albert M. Young | 2023-06-13 |
| 11652156 | Nanosheet transistor with asymmetric gate stack | Ruilong Xie, Carl Radens, Kangguo Cheng, Juntao Li, Dechao Guo +1 more | 2023-05-16 |
| 11605673 | Dual resistive random-access memory with two transistors | Alexander Reznicek, Takashi Ando, Bahman Hekmatshoartabari | 2023-03-14 |
| 11562908 | Dielectric structure to prevent hard mask erosion | Tao Li, Ekmini Anuja De Silva, Praveen Joseph | 2023-01-24 |
| 11557675 | Reduction of bottom epitaxy parasitics for vertical transport field effect transistors | Tao Li, Ruilong Xie, Alexander Reznicek | 2023-01-17 |
| 11271107 | Reduction of bottom epitaxy parasitics for vertical transport field effect transistors | Tao Li, Ruilong Xie, Alexander Reznicek | 2022-03-08 |
| 11251288 | Nanosheet transistor with asymmetric gate stack | Ruilong Xie, Carl Radens, Kangguo Cheng, Juntao Li, Dechao Guo +1 more | 2022-02-15 |
| 11251301 | Cross-bar vertical transport field effect transistors without corner rounding | Ruilong Xie, Tao Li, Alexander Reznicek | 2022-02-15 |
| 11251182 | Staggered stacked vertical crystalline semiconducting channels | Tao Li, Ardasheir Rahman, Praveen Joseph, Indira Seshadri, Ekmini Anuja De Silva | 2022-02-15 |
| 11227922 | Sloped epitaxy buried contact | Tao Li, Ruilong Xie, Alexander Reznicek, Oleg Gluschenkov | 2022-01-18 |