Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11430651 | Nanosheet transistors with sharp junctions | Kangguo Cheng, Lawrence A. Clevenger, John H. Zhang | 2022-08-30 |
| 11355633 | Vertical field effect transistor with bottom source-drain region | Alexander Reznicek, Ruilong Xie, Chun-Chen Yeh | 2022-06-07 |
| 11302637 | Interconnects including dual-metal vias | Devika Sil, Takeshi Nogami | 2022-04-12 |
| 11189528 | Subtractive RIE interconnect | John C. Arnold, Takeshi Nogami | 2021-11-30 |
| 11171054 | Selective deposition with SAM for fully aligned via | Son V. Nguyen, Rudy J. Wojtecki, Noel Arellano, Alexander Edward Hess, Thomas J. Haigh, Jr. +1 more | 2021-11-09 |
| 11164782 | Self-aligned gate contact compatible cross couple contact formation | Ruilong Xie, Dechao Guo, Nicolas Loubet, Alexander Reznicek | 2021-11-02 |
| 11152464 | Self-aligned isolation for nanosheet transistor | Ruilong Xie, Veeraraghavan S. Basker, Robert R. Robison | 2021-10-19 |
| 11133217 | Late gate cut with optimized contact trench size | Alexander Reznicek, Praneet Adusumilli, Ruilong Xie | 2021-09-28 |
| 10872809 | Contact structures for integrated circuit products | Ruilong Xie, Lars Liebmann, Veeraraghavan S. Basker | 2020-12-22 |
| 10600638 | Nanosheet transistors with sharp junctions | Kangguo Cheng, Lawrence A. Clevenger, John H. Zhang | 2020-03-24 |
| 10586741 | Gate height and spacer uniformity | Kangguo Cheng, Lawrence A. Clevenger, John H. Zhang | 2020-03-10 |
| 10497612 | Methods of forming contact structures on integrated circuit products | Ruilong Xie, Lars Liebmann, Veeraraghavan S. Basker | 2019-12-03 |
| 9741609 | Middle of line cobalt interconnection | Kangguo Cheng, Lawrence A. Clevenger, John H. Zhang | 2017-08-22 |
| 9704991 | Gate height and spacer uniformity | Kangguo Cheng, Lawrence A. Clevenger, John H. Zhang | 2017-07-11 |
| 9455254 | Methods of forming a combined gate and source/drain contact structure and the resulting device | Ruilong Xie, Andre P. Labonte, Su Chen Fan | 2016-09-27 |
| 8957465 | Formation of the dielectric cap layer for a replacement gate structure | Ruilong Xie, David V. Horak, Su Chen Fan | 2015-02-17 |
| 8772168 | Formation of the dielectric cap layer for a replacement gate structure | Ruilong Xie, David V. Horak, Su Chen Fan | 2014-07-08 |
| 8698318 | Superfilled metal contact vias for semiconductor devices | James J. Kelly, Veeraraghavan S. Basker, Soon-Cheon Seo, Tuan A. Vo | 2014-04-15 |
| 8334090 | Mixed lithography with dual resist and a single pattern transfer | Nicholas C. M. Fuller, Michael A. Guillorn, Jyotica V. Patel | 2012-12-18 |
| 8101518 | Method and process for forming a self-aligned silicide contact | Cyril Cabral, Jr., Michael A. Cobb, Asa Frye, Randolph F. Knarr, Mahadevaiyer Krishnan +5 more | 2012-01-24 |
| 7914970 | Mixed lithography with dual resist and a single pattern transfer | Nicholas C. M. Fuller, Michael A. Guillorn, Jyotica V. Patel | 2011-03-29 |
| 7544610 | Method and process for forming a self-aligned silicide contact | Cyril Cabral, Jr., Michael A. Cobb, Asa Frye, Randolph F. Knarr, Mahadevaiyer Krishnan +5 more | 2009-06-09 |
| 7501345 | Selective silicide formation by electrodeposit displacement reaction | Veeraraghaven S. Basker, Hariklia Deligianni, James J. Kelly, Christian Lavoie, George G. Totir | 2009-03-10 |