Issued Patents All Time
Showing 25 most recent of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12158605 | Method for manufacturing optical device structures | Levent Colak, Ludovic Godet | 2024-12-03 |
| 12013566 | Method for manufacturing optical device structures | Levent Colak, Ludovic Godet | 2024-06-18 |
| 11487058 | Method for manufacturing optical device structures | Levent Colak, Ludovic Godet | 2022-11-01 |
| 11380581 | Interconnect structures of semiconductor devices having a via structure through an upper conductive line | Catherine B. Labelle, Chanro Park | 2022-07-05 |
| 11112694 | Methods of forming variable-depth device structures | Ludovic Godet, Rutger Meyer Timmerman Thijssen | 2021-09-07 |
| 10879375 | Gate tie-down enablement with inner spacer | Su Chen Fan, Lars Liebmann, Sanjay C. Mehta | 2020-12-29 |
| 10879073 | Insulating gate separation structure for transistor devices | Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos | 2020-12-29 |
| 10832961 | Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor | Su Chen Fan, Ruilong Xie, Veeraraghavan S. Basker, Chanro Park | 2020-11-10 |
| 10832944 | Interconnect structure having reduced resistance variation and method of forming same | Nicholas V. LiCausi, Chanro Park, Ruilong Xie | 2020-11-10 |
| 10790376 | Contact structures | Ruilong Xie, Chanro Park, Julien Frougier, Kangguo Cheng | 2020-09-29 |
| 10770585 | Self-aligned buried contact for vertical field-effect transistor and method of production thereof | Ruilong Xie, Chanro Park, Daniel Chanemougame | 2020-09-08 |
| 10566201 | Gate cut method after source/drain metallization | Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos | 2020-02-18 |
| 10522654 | Gate tie-down enablement with inner spacer | Su Chen Fan, Lars Liebmann, Sanjay C. Mehta | 2019-12-31 |
| 10468300 | Contacting source and drain of a transistor device | Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Chanro Park, Nigel G. Cave +1 more | 2019-11-05 |
| 10388602 | Local interconnect structure including non-eroded contact via trenches | Su Chen Fan, Vimal Kamineni, Ruilong Xie | 2019-08-20 |
| 10332977 | Gate tie-down enablement with inner spacer | Su Chen Fan, Lars Liebmann, Sanjay C. Mehta | 2019-06-25 |
| 10283408 | Middle of the line (MOL) contacts with two-dimensional self-alignment | Ruilong Xie, Chanro Park, Lars Liebmann | 2019-05-07 |
| 10249728 | Air-gap gate sidewall spacer and method | Daniel Chanemougame, Ruilong Xie, Lars Liebmann, Nigel G. Cave, Guillaume Bouche | 2019-04-02 |
| 10243053 | Gate contact structure positioned above an active region of a transistor device | Ruilong Xie, Chanro Park | 2019-03-26 |
| 10211100 | Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistor | Ruilong Xie, Lars Liebmann, Nigel G. Cave, Nicholas V. LiCausi, Guillaume Bouche +1 more | 2019-02-19 |
| 10204994 | Methods of forming a semiconductor device with a gate contact positioned above the active region | Ruilong Xie, Chanro Park, Lars Liebmann, Nigel G. Cave, Mark V. Raymond +2 more | 2019-02-12 |
| 10128352 | Gate tie-down enablement with inner spacer | Su Chen Fan, Lars Liebmann, Sanjay C. Mehta | 2018-11-13 |
| 10026824 | Air-gap gate sidewall spacer and method | Daniel Chanemougame, Ruilong Xie, Lars Liebmann, Nigel G. Cave, Guillaume Bouche | 2018-07-17 |
| 10014215 | Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps | Ruilong Xie, Xunyuan Zhang | 2018-07-03 |
| 9947589 | Methods of forming a gate contact for a transistor above an active region and the resulting device | Chanro Park, Ruilong Xie, Lars Liebmann, Nigel G. Cave, Mark V. Raymond | 2018-04-17 |