| 12446291 |
Inverted top-tier FET for multi-tier gate-on-gate 3-dimension integration (3Di) |
Daniel Chanemougame, Jeffrey Smith, Paul Gutwin, Xiuqin Xu |
2025-10-14 |
|
| 12414367 |
Tapered device for lateral gate all around devices |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin |
2025-09-09 |
|
| 12354991 |
Replacement buried power rail in backside power delivery |
Hoyoung Kang, Jeffrey Smith, Anton J. deVilliers, Daniel Chanemougame |
2025-07-08 |
|
| 12336274 |
Self-aligned method for vertical recess for 3D device integration |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Subhadeep Kal, Kandabara Tapily +1 more |
2025-06-17 |
|
| 12237333 |
Power wall integration for multiple stacked devices |
Daniel Chanemougame, Jeffrey Smith |
2025-02-25 |
|
| 12224281 |
Interdigitated device stack |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline, Xiaoqing Xu +1 more |
2025-02-11 |
|
| 12218066 |
Monolithic formation of a set of interconnects below active devices |
Daniel Chanemougame, Jeffrey Smith |
2025-02-04 |
|
| 12218135 |
Wiring in diffusion breaks in an integrated circuit |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin |
2025-02-04 |
|
| 12176293 |
Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline, Xiaoqing Xu +1 more |
2024-12-24 |
|
| 12142516 |
Self aligned buried power rail |
Nicholas V. LiCausi, Guillaume Bouche |
2024-11-12 |
$72,106,000 |
| 12131994 |
Metallization lines on integrated circuit products |
Ruilong Xie, Daniel Chanemougame, Geng Han |
2024-10-29 |
$40,018,000 |
| 12087640 |
High density logic formation using multi-dimensional laser annealing |
H. Jim Fulford, Mark I. Gardner, Jeffrey Smith, Daniel Chanemougame |
2024-09-10 |
|
| 12051638 |
Integrated high efficiency transistor cooling |
Daniel Chanemougame, Jeffrey Smith, Paul Gutwin |
2024-07-30 |
|
| 12040271 |
Power delivery network for CFET with buried power rails |
Jeffrey Smith, Daniel Chanemougame, Anton J. deVilliers |
2024-07-16 |
|
| 12020990 |
Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks |
Jeffrey Smith, Kandabara Tapily, Daniel Chanemougame, Mark I. Gardner, H. Jim Fulford +1 more |
2024-06-25 |
|
| 12014984 |
Method of manufacturing a semiconductor apparatus having stacked devices |
Jeffrey Smith, Anton J. deVilliers |
2024-06-18 |
|
| 12002869 |
Gate contact structures and cross-coupled contact structures for transistor devices |
Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Heimanu Niebojewski +3 more |
2024-06-04 |
$66,584,000 |
| 12002862 |
Inter-level handshake for dense 3D logic integration |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin |
2024-06-04 |
|
| 11961802 |
Power-tap pass-through to connect a buried power rail to front-side power distribution network |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin |
2024-04-16 |
|
| 11923364 |
Double cross-couple for two-row flip-flop using CFET |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin |
2024-03-05 |
|
| 11901360 |
Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory |
Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily |
2024-02-13 |
|
| 11830852 |
Multi-tier backside power delivery network for dense gate-on-gate 3D logic |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline, Xiaoqing Xu +1 more |
2023-11-28 |
|
| 11791263 |
Metallization lines on integrated circuit products |
Ruilong Xie, Daniel Chanemougame, Geng Han |
2023-10-17 |
$50,124,000 |
| 11791271 |
Monolithic formation of a set of interconnects below active devices |
Daniel Chanemougame, Jeffrey Smith |
2023-10-17 |
|
| 11764113 |
Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds |
Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Robert D. Clark, Anton J. deVilliers |
2023-09-19 |
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