Issued Patents All Time
Showing 25 most recent of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432936 | Capacitor integrated with memory element of memory cell | Venkatesh P. Gopinath, Joseph Versaggi, Gregory A. Northrop | 2025-09-30 |
| 12376315 | Resistive memory element arrays with shared electrode strips | Venkatesh P. Gopinath, Xiaoli Hu | 2025-07-29 |
| 12328880 | Hierarchical memory architecture including on-chip multi-bank non-volatile memory with low leakage and low latency | Navneet Jain, Shashank Nemawarkar | 2025-06-10 |
| 12293086 | Apparatus and method for providing high throughput memory responses | Shashank Nemawarkar | 2025-05-06 |
| 12176023 | Non-volatile static random access memory bit cells with ferroelectric field-effect transistors | Pirooz Parvarandeh, Venkatesh P. Gopinath, Navneet Jain, Halid Mulaosmanovic | 2024-12-24 |
| 12087384 | Bias voltage generation circuit for memory devices | Ming Yin, Nishtha Gaul, Shashank Nemawarkar | 2024-09-10 |
| 12051465 | Sense circuit and high-speed memory structure incorporating the sense circuit | Chandrahasa Reddy Dinnipati, Ramesh Raghavan | 2024-07-30 |
| 12002869 | Gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Lars Liebmann, Heimanu Niebojewski +3 more | 2024-06-04 |
| 11881241 | Resistive memory array with localized reference cells | Chandrahasa Reddy Dinnipati, Ramesh Raghavan | 2024-01-23 |
| 11776606 | Sensing scheme for STT-MRAM using low-barrier nanomagnets | Amogh Agrawal, Ajey Poovannummoottil Jacob | 2023-10-03 |
| 11735257 | Memory with high-accuracy reference-free multi-inverter sense circuit and associated sensing method | Nishtha Gaul, Akhilesh Jaiswal | 2023-08-22 |
| 11587601 | Apparatus and method for controlled transmitting of read pulse and write pulse in memory | Shashank Nemawarkar | 2023-02-21 |
| 11475941 | Non-volatile transistor embedded static random access memory (SRAM) cell | Akhilesh Jaiswal, Steven R. Soss | 2022-10-18 |
| 11469309 | Gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Lars Liebmann, Heimanu Niebojewski +3 more | 2022-10-11 |
| 11435982 | True random number generation and physically unclonable functions using voltage control of magnetic anisotropy effects in STT-MRAM | Hemant Dixit, Julien Frougier, William J. Taylor, Jr. | 2022-09-06 |
| 11309319 | Structures and SRAM bit cells integrating complementary field-effect transistors | Randy W. Mann, Julien Frougier, Ruilong Xie | 2022-04-19 |
| 11227894 | Memory cells with vertically overlapping wordlines | Anuj Gupta | 2022-01-18 |
| 11201152 | Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor | Ruilong Xie, Steven R. Soss, Steven Bentley, Daniel Chanemougame, Julien Frougier +1 more | 2021-12-14 |
| 11120857 | Low variability reference parameter generation for magnetic random access memory | Akhilesh Jaiswal | 2021-09-14 |
| 11087814 | Sensing scheme for STT-MRAM using low-barrier nanomagnets | Amogh Agrawal, Ajey Poovannummoottil Jacob | 2021-08-10 |
| 11075247 | Circuit structure and method for resistive RAM with self aligned contacts in zero-via layer | Anuj Gupta, Joe A. Versaggi | 2021-07-27 |
| 11004509 | Circuit structure and memory circuit with resistive memory elements, and related methods | Steven R. Soss | 2021-05-11 |
| 11004491 | Twisted wordline structures | Anuj Gupta, Joseph Versaggi | 2021-05-11 |
| 10950610 | Asymmetric gate cut isolation for SRAM | Ruilong Xie, Julien Frougier, Daniel Chanemougame, Hui Zang | 2021-03-16 |
| 10840146 | Structures and SRAM bit cells with a buried cross-couple interconnect | Julien Frougier, Ruilong Xie | 2020-11-17 |