Issued Patents All Time
Showing 1–25 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11934021 | Photonic devices integrated with thermally conductive layers | Hemant Dixit, Yusheng Bian, Theodore Letavic, Oscar D. Restrepo | 2024-03-19 |
| 11855074 | Electrostatic discharge devices | Zhiqing Li, Anindya Nath | 2023-12-26 |
| 11543604 | On-chip heater with a heating element that locally generates different amounts of heat and methods | — | 2023-01-03 |
| 11538815 | Non-volatile memory cell arrays with a sectioned active region and methods of manufacturing thereof | Oscar D. Restrepo, Edmund K. Banghart | 2022-12-27 |
| 11435982 | True random number generation and physically unclonable functions using voltage control of magnetic anisotropy effects in STT-MRAM | Hemant Dixit, Julien Frougier, Bipul C. Paul | 2022-09-06 |
| 11387353 | Structure providing charge controlled electronic fuse | Jagar Singh, Sudarshan Narayanan, Alvin J. Joseph, Jeffrey B. Johnson | 2022-07-12 |
| 10665590 | Wrap-around contact surrounding epitaxial regions of integrated circuit structures and method of forming same | Ruilong Xie, Hui Zang | 2020-05-26 |
| 10515679 | Magneto-resistive memory structures with improved sensing, and associated sensing methods | Akhilesh Jaiswal, Ajey Poovannummoottil Jacob, Bipul C. Paul, Danny Pak-Chum Shum | 2019-12-24 |
| 10510392 | Integrated circuits having memory cells with shared bit lines and shared source lines | Bipul C. Paul, Akhilesh Jaiswal, Ajey Poovannummoottil Jacob, Danny Pak-Chum Shum | 2019-12-17 |
| 10050118 | Semiconductor device configured for avoiding electrical shorting | Ruilong Xie, Ryan Ryoung-Han Kim, Chanro Park, John A. Iacoponi | 2018-08-14 |
| 9793171 | Buried source-drain contact for integrated circuit transistor devices and method of making same | Qing Liu, Ruilong Xie, Chun-Chen Yeh, Xiuyu Cai | 2017-10-17 |
| 9786607 | Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer | Su Chen Fan, Sukwon Hong | 2017-10-10 |
| 9728456 | Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer | Su Chen Fan, Sukwon Hong | 2017-08-08 |
| 9583442 | Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer | Su Chen Fan, Sukwon Hong | 2017-02-28 |
| 9461171 | Methods of increasing silicide to epi contact areas and the resulting devices | Ruilong Xie, Hoon Kim, Naim Moumen, Chanro Park | 2016-10-04 |
| 9385201 | Buried source-drain contact for integrated circuit transistor devices and method of making same | Qing Liu, Ruilong Xie, Chun-Chen Yeh, Xiuyu Cai | 2016-07-05 |
| 9362403 | Buried fin contact structures on FinFET semiconductor devices | Ruilong Xie, Ryan Ryoung-Han Kim | 2016-06-07 |
| 9362279 | Contact formation for semiconductor device | Ruilong Xie, Andy Wei, Ryan Ryoung-Han Kim, Kwan-Yong Lim, Chanro Park | 2016-06-07 |
| 9330972 | Methods of forming contact structures for semiconductor devices and the resulting devices | Ruilong Xie, Vimal Kamineni | 2016-05-03 |
| 9318552 | Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices | Ruilong Xie, Ajey Poovannummoottil Jacob | 2016-04-19 |
| 9312182 | Forming gate and source/drain contact openings by performing a common etch patterning process | Ruilong Xie, Min Gyu Sung | 2016-04-12 |
| 9299781 | Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material | Ruilong Xie, Ryan Ryoung-Han Kim | 2016-03-29 |
| 9263340 | Methods for removing selected fins that are formed for finFET semiconductor devices | Ruilong Xie | 2016-02-16 |
| 9231051 | Methods of forming spacers on FinFETs and other semiconductor devices | Xiuyu Cai, Ruilong Xie | 2016-01-05 |
| 9202918 | Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices | Ruilong Xie, Ryan Ryoung-Han Kim | 2015-12-01 |