Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11270912 | Method for forming a via hole self-aligned with a metal block on a substrate | Martin O'Toole, Christopher Wilson, Zsolt Tokei | 2022-03-08 |
| 11092884 | Mask for extreme-ultraviolet (extreme-UV) lithography and method for manufacturing the same | Jae Uk Lee | 2021-08-17 |
| 10978335 | Method for producing a gate cut structure on an array of semiconductor fins | Boon Teik Chan, Efrain Altamirano Sanchez | 2021-04-13 |
| 10592632 | Method for analyzing design of an integrated circuit | Jae Uk Lee | 2020-03-17 |
| 10580779 | Vertical transistor static random access memory cell | Kwan-Yong Lim | 2020-03-03 |
| 10283505 | Dummy gate used as interconnection and method of making the same | Wenhui Wang, Linus Jang, Jason R. Cantone, Lei Sun, Seowoo Nam | 2019-05-07 |
| 10192792 | Method of utilizing trench silicide in a gate cross-couple construct | — | 2019-01-29 |
| 10153162 | Shrink process aware assist features | Wenhui Wang, Azat Latypov, Tamer Coskun, Lei Sun | 2018-12-11 |
| 10147637 | Methods for forming conductive paths and vias | Youssef Drissi, Stephane Lariviere, Praveen Raghavan, Darko Trivkovic | 2018-12-04 |
| 10103066 | Method of utilizing trench silicide in a gate cross-couple construct | — | 2018-10-16 |
| 10050118 | Semiconductor device configured for avoiding electrical shorting | Ruilong Xie, Chanro Park, William J. Taylor, Jr., John A. Iacoponi | 2018-08-14 |
| 9953834 | Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines | Lei Sun, Ruilong Xie, Xunyuan Zhang | 2018-04-24 |
| 9865704 | Single and double diffusion breaks on integrated circuit products comprised of FinFET devices | Ruilong Xie, Kwan-Yong Lim, Min Gyu Sung | 2018-01-09 |
| 9859120 | Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines | Lei Sun, Ruilong Xie, Xunyuan Zhang | 2018-01-02 |
| 9711511 | Vertical channel transistor-based semiconductor memory structure | Kwan-Yong Lim, Motoi Ichihashi, Youngtag Woo, Deepak Nayak | 2017-07-18 |
| 9651855 | Methods for optical proximity correction in the design and fabrication of integrated circuits using extreme ultraviolet lithography | Lei Sun, Wenhui Wang | 2017-05-16 |
| 9595478 | Dummy gate used as interconnection and method of making the same | Wenhui Wang, Linus Jang, Jason R. Cantone, Lei Sun, Seowoo Nam | 2017-03-14 |
| 9553028 | Methods of forming reduced resistance local interconnect structures and the resulting devices | Ruilong Xie | 2017-01-24 |
| 9543416 | Methods of forming products with FinFET semiconductor devices without removing fins in certain areas of the product | Min Gyu Sung | 2017-01-10 |
| 9490317 | Gate contact structure having gate contact layer | Andre P. Labonte | 2016-11-08 |
| 9484258 | Method for producing self-aligned vias | Wenhui Wang, Lei Sun, Erik Verduijn, Yulu Chen | 2016-11-01 |
| 9478462 | SAV using selective SAQP/SADP | Wenhui Wang, Lei Sun, Erik Verduijn, Yulu Chen | 2016-10-25 |
| 9466604 | Metal segments as landing pads and local interconnects in an IC device | Youngtag Woo, Myungjun Lee, Jongwook Kye | 2016-10-11 |
| 9460079 | Method, system and recording medium for providing dictionary function and file distribution system | Tae Hoon Lee, Jonghwan Kim, Eunjoo Jeon, Jin An JUNG, Taihwa Hong +2 more | 2016-10-04 |
| 9449835 | Methods of forming features having differing pitch spacing and critical dimensions | Linus Jang | 2016-09-20 |