Issued Patents All Time
Showing 25 most recent of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10050118 | Semiconductor device configured for avoiding electrical shorting | Ruilong Xie, Ryan Ryoung-Han Kim, Chanro Park, William J. Taylor, Jr. | 2018-08-14 |
| 9318436 | Copper based nitride liner passivation layers for conductive copper structures | Xunyuan Zhang, Larry Zhao, Ming He, Sean Xuan Lin, Errol Todd Ryan | 2016-04-19 |
| 9117877 | Methods of forming a dielectric cap layer on a metal gate structure | Xiuyu Cai, Ruilong Xie, Jin Cho | 2015-08-25 |
| 9087881 | Electroless fill of trench in semiconductor structure | Sean Xuan Lin, Xunyuan Zhang, Ming He, Larry Zhao, Kunaljeet Tanwar | 2015-07-21 |
| 8946075 | Methods of forming semiconductor device with self-aligned contact elements and the resulting devices | Xiuyu Cai, Ruilong Xie | 2015-02-03 |
| 8940633 | Methods of forming semiconductor device with self-aligned contact elements and the resulting devices | Xiuyu Cai, Ruilong Xie | 2015-01-27 |
| 8859419 | Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device | Xunyuan Zhang, Larry Zhao, Ming He, Sean Xuan Lin, Errol Todd Ryan | 2014-10-14 |
| 8753975 | Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device | Xunyuan Zhang, Larry Zhao, Ming He, Sean Xuan Lin, Errol Todd Ryan | 2014-06-17 |
| 8728908 | Methods of forming a dielectric cap layer on a metal gate structure | Ruilong Xie, Chang Seo Park, William James Taylor, III | 2014-05-20 |
| 8691696 | Methods for forming an integrated circuit with straightened recess profile | Xiuyu Cai, Xunyuan Zhang, Ruilong Xie, Errol Todd Ryan | 2014-04-08 |
| 8592312 | Method for depositing a conductive capping layer on metal lines | E. Todd Ryan | 2013-11-26 |
| 8105943 | Enhancing structural integrity and defining critical dimensions of metallization systems of semiconductor devices by using ALD techniques | Christof Streck, Volker Kahlert | 2012-01-31 |
| 7759205 | Methods for fabricating semiconductor devices minimizing under-oxide regrowth | Kingsuk Maitra | 2010-07-20 |
| 7557035 | Method of forming semiconductor devices by microwave curing of low-k dielectric films | E. Todd Ryan | 2009-07-07 |
| 6809032 | Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques | Frank Mauersberger, Peter J. Beckage, Paul R. Besser, Frederick N. Hause, Errol Todd Ryan +1 more | 2004-10-26 |
| 6690580 | Integrated circuit structure with dielectric islands in metallized regions | Cindy Goldberg | 2004-02-10 |
| 6649533 | Method and apparatus for forming an under bump metallurgy layer | — | 2003-11-18 |
| 6555396 | Method and apparatus for enhancing endpoint detection of a via etch | Ailian Zhao, Thomas E. Spikes, Jr. | 2003-04-29 |
| 6555479 | Method for forming openings for conductive interconnects | Frederick N. Hause, Paul R. Besser, Frank Mauersberger, Errol Todd Ryan, William S. Brennan +1 more | 2003-04-29 |
| 6514858 | Test structure for providing depth of polish feedback | Frederick N. Hause, Paul R. Besser, Frank Mauersberger, Errol Todd Ryan, William S. Brennan +1 more | 2003-02-04 |
| 6489240 | Method for forming copper interconnects | Paul R. Besser, Frederick N. Hause, Frank Mauersberger, Errol Todd Ryan, William S. Brennan +1 more | 2002-12-03 |
| 6489683 | Variable grain size in conductors for semiconductor vias and trenches | Sergey Lopatin | 2002-12-03 |
| 6468889 | Backside contact for integrated circuit and method of forming same | John C. Miethke | 2002-10-22 |
| 6448099 | Method and apparatus for detecting voltage contrast in a semiconductor wafer | Tom Spikes, Jr., John C. Miethke | 2002-09-10 |
| 6413846 | Contact each methodology and integration scheme | Paul R. Besser, Errol Todd Ryan, Frederick N. Hause, Frank Mauersberger, William S. Brennan +1 more | 2002-07-02 |