Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12346412 | Interfaces for assisted defect recognition systems | Joseph Schlecht, Caleb Nelson Hay, Eric Ferley | 2025-07-01 |
| RE49820 | Semiconductor device having a self-forming barrier layer at via bottom | Larry Zhao, Ming He, Xunyuan Zhang | 2024-01-30 |
| 11619597 | Dual robot control systems for non-destructive evaluation | Joseph Schlecht, Caleb Nelson Hay, Jackson Turner, Sean Anderson, Kirk Guillaume +1 more | 2023-04-04 |
| 10879098 | Semiconductor chip holder | Tsung-Jen Liao, Pei-Haw Tsao, Tsui-Mei Chen, Yu-Jung LIN, Ju-Min Chen | 2020-12-29 |
| 10727120 | Controlling back-end-of-line dimensions of semiconductor devices | Ruilong Xie, Guoxiang Ning, Lei Sun | 2020-07-28 |
| 10580696 | Interconnects formed by a metal displacement reaction | Christian Witt, Mark V. Raymond, Nicholas V. LiCausi, Errol Todd Ryan | 2020-03-03 |
| 10573593 | Metal interconnects for super (skip) via integration | Xunyuan Zhang, Shao Beng Law, James Jay McMahon | 2020-02-25 |
| RE47630 | Semiconductor device having a self-forming barrier layer at via bottom | Larry Zhao, Ming He, Xunyuan Zhang | 2019-10-01 |
| 10395926 | Multiple patterning with mandrel cuts formed using a block mask | Minghao Tang, Yuping Ren, Shao Beng Law, Genevieve Beique, Xun XIANG +1 more | 2019-08-27 |
| 10283372 | Interconnects formed by a metal replacement process | Xunyuan Zhang, Mark V. Raymond, Errol Todd Ryan, Nicholas V. LiCausi | 2019-05-07 |
| 10181421 | Liner recess for fully aligned via | Errol Todd Ryan | 2019-01-15 |
| 10134580 | Metallization levels and methods of making thereof | Nicholas V. LiCausi, Errol Todd Ryan | 2018-11-20 |
| 10109490 | Cobalt interconnects formed by selective bottom-up fill | Xunyuan Zhang | 2018-10-23 |
| 10103029 | Process for filling vias in the microelectronics | Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, Jr. +2 more | 2018-10-16 |
| 10026687 | Metal interconnects for super (skip) via integration | Xunyuan Zhang, Shao Beng Law, James Jay McMahon | 2018-07-17 |
| 9853110 | Method of forming a gate contact structure for a semiconductor device | Xunyuan Zhang, Ruilong Xie | 2017-12-26 |
| 9831100 | Solution based etching of titanium carbide and titanium nitride structures | John Foster, Muthumanickam Sankarapandian, Ruilong Xie | 2017-11-28 |
| 9805972 | Skip via structures | Xunyuan Zhang, James Jay McMahon, Shao Beng Law | 2017-10-31 |
| 9520321 | Integrated circuits and methods for fabricating integrated circuits with self-aligned vias | Errol Todd Ryan | 2016-12-13 |
| 9439565 | Wireless viewing of digital pathology specimens | Gary Chai, Ben Wei Chen | 2016-09-13 |
| 9425103 | Methods of using a metal protection layer to form replacement gate structures for semiconductor devices | Ruilong Xie, Chanro Park | 2016-08-23 |
| 9318436 | Copper based nitride liner passivation layers for conductive copper structures | Xunyuan Zhang, Larry Zhao, Ming He, John A. Iacoponi, Errol Todd Ryan | 2016-04-19 |
| 9299745 | Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same | Xunyuan Zhang, Kunaljeet Tanwar | 2016-03-29 |
| 9263327 | Minimizing void formation in semiconductor vias and trenches | Xunyuan Zhang | 2016-02-16 |
| 9087881 | Electroless fill of trench in semiconductor structure | Xunyuan Zhang, Ming He, Larry Zhao, John A. Iacoponi, Kunaljeet Tanwar | 2015-07-21 |