Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11651992 | Gap fill void and connection structures | Haigou Huang, Yuping Ren, Paul Ackmann | 2023-05-16 |
| 11037937 | SRAM bit cells formed with dummy structures | Meixiong Zhao, Randy W. Mann, Sanjay R. Parihar, Anton V. Tokranov, Hong Yu +1 more | 2021-06-15 |
| 10957701 | Fin-based anti-fuse device for integrated circuit (IC) products, methods of making such an anti-fuse device and IC products comprising such an anti-fuse device | Hongliang Shen, Meixiong Zhao | 2021-03-23 |
| 10923388 | Gap fill void and connection structures | Haigou Huang, Yuping Ren, Paul Ackmann | 2021-02-16 |
| 10896874 | Interconnects separated by a dielectric region formed using removable sacrificial plugs | Ruilong Xie, Lei Sun | 2021-01-19 |
| 10892222 | Anti-fuse for an integrated circuit (IC) product and method of making such an anti-fuse for an IC product | Erfeng Ding, Meixiong Zhao | 2021-01-12 |
| 10816483 | Double pass diluted ultraviolet reticle inspection | Jed H. Rankin, Paul Ackmann, Jung-Yu Hsieh, Ming Lei | 2020-10-27 |
| 10804170 | Device/health of line (HOL) aware eBeam based overlay (EBO OVL) structure | Hongliang Shen, Erfeng Ding, Dongsuk Park, Xiaoxiao Zhang, Lan Yang | 2020-10-13 |
| 10777413 | Interconnects with non-mandrel cuts formed by early block patterning | Yuping Ren, Haigou Huang, Sunil Kumar Singh | 2020-09-15 |
| 10770344 | Chamferless interconnect vias of semiconductor devices | Yuping Ren, Haigou Huang, Ravi Prakash Srivastava, Zhiguo Sun, Qiang Fang +1 more | 2020-09-08 |
| 10727120 | Controlling back-end-of-line dimensions of semiconductor devices | Sean Xuan Lin, Ruilong Xie, Lei Sun | 2020-07-28 |
| 10714422 | Anti-fuse with self aligned via patterning | Xiaoqiang Zhang, Jiehui Shu | 2020-07-14 |
| 10642160 | Self-aligned quadruple patterning pitch walking solution | Lei Sun, Meixiong Zhao, Erfeng Ding | 2020-05-05 |
| 10627720 | Overlay mark structures | Lei Sun, John H. Zhang, Shao Beng Law, Xunyuan Zhang, Ruilong Xie | 2020-04-21 |
| 10483214 | Overlay structures | Xintuo Dai, Dongsuk Park, Mert Karakoy | 2019-11-19 |
| 10423078 | FinFET cut isolation opening revision to compensate for overlay inaccuracy | Hongliang Shen, Erfeng Ding | 2019-09-24 |
| 10386726 | Geometry vectorization for mask process correction | Liang Cao, Wenchao Jiang, Jie Zhang | 2019-08-20 |
| 10332745 | Dummy assist features for pattern support | Lei Sun, Ruilong Xie, Wenhui Wang, Yulu Chen, Erik Verduijn +2 more | 2019-06-25 |
| 10324381 | FinFET cut isolation opening revision to compensate for overlay inaccuracy | Hongliang Shen, Erfeng Ding | 2019-06-18 |
| 10199271 | Self-aligned metal wire on contact structure and method for forming same | Ruilong Xie, Guillaume Bouche, Laertis Economikos, Lei Sun, Xunyuan Zhang | 2019-02-05 |
| 10002827 | Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device | Yuping Ren, Chin Teong Lim, Xusheng Wu, Paul Ackmann | 2018-06-19 |
| 9864831 | Metrology pattern layout and method of use thereof | Guido Ueberreiter, Lloyd C. Litt, Paul Ackmann | 2018-01-09 |
| 9817940 | Method wherein test cells and dummy cells are included into a layout of an integrated circuit | Guido Ueberreiter, Paul Ackmann, Jui-Hsuan Feng, Chin Teong Lim | 2017-11-14 |
| 9791772 | Monitoring pattern for devices | Paul Ackmann, Byoung Il Choi | 2017-10-17 |
| 9672313 | Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device | Yuping Ren, Chin Teong Lim, Xusheng Wu, Paul Ackmann | 2017-06-06 |