| 6599174 |
Eliminating dishing non-uniformity of a process layer |
— |
2003-07-29 |
$3,092,000 |
| 6555396 |
Method and apparatus for enhancing endpoint detection of a via etch |
Ailian Zhao, John A. Iacoponi |
2003-04-29 |
$1,822,000 |
| 6458678 |
Transistor formed using a dual metal process for gate and source/drain region |
Frederick N. Hause, David Wu |
2002-10-01 |
$734,000 |
| 6326251 |
Method of making salicidation of source and drain regions with metal gate MOSFET |
Mark I. Gardner, H. Jim Fulford |
2001-12-04 |
$4,361,000 |
| 6309936 |
Integrated formation of LDD and non-LDD semiconductor devices |
Mark I. Gardner, Robert Paiz |
2001-10-30 |
$4,666,000 |
| 6271112 |
Interlayer between titanium nitride and high density plasma oxide |
Christopher Wooten, Craig W. Christian, Allen L. Evans, Tim Z. Hossain |
2001-08-07 |
$4,984,000 |
| 6239476 |
Integrated circuit isolation structure employing a protective layer and method for making same |
Mark I. Gardner, H. Jim Fulford |
2001-05-29 |
$6,079,000 |
| 6228724 |
Method of making high performance MOSFET with enhanced gate oxide integration and device formed thereby |
Mark I. Gardner, H. Jim Fulford |
2001-05-08 |
$6,632,000 |
| 6225201 |
Ultra short transistor channel length dictated by the width of a sidewall spacer |
Mark I. Gardner, Derrick J. Wristers, Jon D. Cheek |
2001-05-01 |
$7,851,000 |
| 6211000 |
Method of making high performance mosfets having high conductivity gate conductors |
Mark I. Gardner, H. Jim Fulford |
2001-04-03 |
$5,058,000 |
| 6194283 |
High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers |
Mark I. Gardner, Robert Paiz |
2001-02-27 |
$7,317,000 |
| 6171917 |
Transistor sidewall spacers composed of silicon nitride CVD deposited from a high density plasma source |
Sey-Ping Sun, Fred N. Hause |
2001-01-09 |
$4,016,000 |
| 6160316 |
Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths |
Mark I. Gardner, Robert Paiz |
2000-12-12 |
$4,351,000 |
| 6140190 |
Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors |
Mark I. Gardner, Michael Duane |
2000-10-31 |
$4,395,000 |
| 6140163 |
Method and apparatus for upper level substrate isolation integrated with bulk silicon |
Mark I. Gardner, Daniel Kadosh |
2000-10-31 |
$4,395,000 |
| 6124174 |
Spacer structure as transistor gate |
Mark I. Gardner |
2000-09-26 |
$6,800,000 |
| 6114219 |
Method of manufacturing an isolation region in a semiconductor device using a flowable oxide-generating material |
Sey-Ping Sun, Robert Dawson |
2000-09-05 |
$8,144,000 |
| 6110785 |
Formulation of high performance transistors using gate trim etch process |
Mark I. Gardner, Anthony J. Toprac |
2000-08-29 |
$7,735,000 |
| 6100204 |
Method of making ultra thin gate oxide using aluminum oxide |
Mark I. Gardner, Mark C. Gilmer |
2000-08-08 |
$4,885,000 |
| 6074904 |
Method and structure for isolating semiconductor devices after transistor formation |
Mark W. Michael, Mark I. Gardner, Robert Dawson |
2000-06-13 |
$9,833,000 |
| 6064102 |
Semiconductor device having gate electrodes with different gate insulators and fabrication thereof |
Mark I. Gardner, H. Jim Fulford |
2000-05-16 |
$14,024,000 |
| 6048766 |
Flash memory device having high permittivity stacked dielectric and fabrication thereof |
Mark I. Gardner, Mark C. Gilmer |
2000-04-11 |
$13,721,000 |
| 6037244 |
Method of manufacturing a semiconductor device using advanced contact formation |
Mark I. Gardner, Robert Paiz, Frederick N. Hause, Sey-Ping Sun |
2000-03-14 |
$8,869,000 |
| 5981354 |
Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process |
Fred N. Hause, Daniel Kadosh |
1999-11-09 |
$2,369,000 |
| 5970375 |
Semiconductor fabrication employing a local interconnect |
Mark I. Gardner, Daniel Kadosh |
1999-10-19 |
$1,257,000 |
