Issued Patents All Time
Showing 25 most recent of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6727569 | Method of making enhanced trench oxide with low temperature nitrogen integration | Mark I. Gardner, Robert Paiz | 2004-04-27 |
| 6373113 | Nitrogenated gate structure for improved transistor performance and method for making same | Mark I. Gardner | 2002-04-16 |
| 6265749 | Metal silicide transistor gate spaced from a semiconductor substrate by a ceramic gate dielectric having a high dielectric constant | Mark I. Gardner | 2001-07-24 |
| 6214123 | Chemical vapor deposition systems and methods for depositing films on semiconductor wafers | Mark I. Gardner, Robert Paiz | 2001-04-10 |
| 6214690 | Method of forming a semiconductor device having integrated electrode and isolation region formation | Mark I. Gardner | 2001-04-10 |
| 6211025 | Method of making elevated source/drain using poly underlayer | Mark I. Gardner | 2001-04-03 |
| 6204130 | Semiconductor device having reduced polysilicon gate electrode width and method of manufacture thereof | Mark I. Gardner | 2001-03-20 |
| 6197644 | High density mosfet fabrication method with integrated device scaling | Mark I. Gardner | 2001-03-06 |
| 6197668 | Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices | Mark I. Gardner | 2001-03-06 |
| 6197647 | Method of forming ultra-thin oxides with low temperature oxidation | Mark I. Gardner | 2001-03-06 |
| 6175144 | Advanced isolation structure for high density semiconductor devices | Mark I. Gardner | 2001-01-16 |
| 6174794 | Method of making high performance MOSFET with polished gate and source/drain feature | Mark I. Gardner | 2001-01-16 |
| 6172402 | Integrated circuit having transistors that include insulative punchthrough regions and method of formation | Mark I. Gardner, Daniel Kadosh | 2001-01-09 |
| 6172407 | Source/drain and lightly doped drain formation at post interlevel dielectric isolation with high-K gate electrode design | Mark I. Gardner | 2001-01-09 |
| 6169306 | Semiconductor devices comprised of one or more epitaxial layers | Mark I. Gardner | 2001-01-02 |
| 6165314 | Apparatus for performing jet vapor reduction of the thickness of process layers | Mark I. Gardner | 2000-12-26 |
| 6163060 | Semiconductor device with a composite gate dielectric layer and gate barrier layer and method of making same | Mark I. Gardner | 2000-12-19 |
| 6153477 | Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant | Mark I. Gardner | 2000-11-28 |
| 6152075 | Method and system for heating semiconductor wafers | Mark I. Gardner | 2000-11-28 |
| 6148832 | Method and apparatus for in-situ cleaning of polysilicon-coated quartz furnaces | Mark I. Gardner, Robert Paiz | 2000-11-21 |
| 6147004 | Jet vapor reduction of the thickness of process layers | Mark I. Gardner | 2000-11-14 |
| 6140191 | Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions | Mark I. Gardner, Robert Paiz | 2000-10-31 |
| 6140167 | High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation | Mark I. Gardner, Frederick N. Hause | 2000-10-31 |
| 6130164 | Semiconductor device having gate oxide formed by selective oxide removal and method of manufacture thereof | Mark I. Gardner | 2000-10-10 |
| 6127284 | Method of manufacturing a semiconductor device having nitrogen-bearing oxide gate insulating layer | Mark I. Gardner | 2000-10-03 |