Issued Patents All Time
Showing 25 most recent of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423502 | Rule check heatmap prediction | Rongjian Liang, Hua Xiang, Jinwook Jung, Lakshmi N. Reddy, Shyam Ramji +2 more | 2025-09-23 |
| 12417333 | Short net pin alignment for routing | Hua Xiang, Benjamin Neil Trombley, Gustavo E. Tellez, Paul G. Villarrubia | 2025-09-16 |
| 12282725 | Enhanced alignment for global placement in a circuit | Alexey Y. Lvov, Benjamin Neil Trombley, Lakshmi N Reddy, Paul G. Villarrubia | 2025-04-22 |
| 12277375 | Power staple avoidance for routing via reduction | Hua Xiang, Benjamin Neil Trombley, Gustavo E. Tellez, Paul G. Villarrubia | 2025-04-15 |
| 12124789 | Multi-stage electronic design automation parameter tuning | Jinwook Jung, Alexey Y. Lvov, Lakshmi N. Reddy, Hua Xiang, Rongjian Liang | 2024-10-22 |
| 11763963 | Power cable | Young Eun Cho, Min-Sang CHO, Sue Jin SON | 2023-09-19 |
| 11629246 | Power cable | Young Eun Cho, Sue Jin SON, Min-Sang CHO, Jung In SHIN | 2023-04-18 |
| 11356275 | Electronically verifying a process flow | Enriquillo Valdez, Richard H. Boivie, Venkata Sitaramagiridharganesh Ganapavarapu, Jinwook Jung, Roman Vaculin +1 more | 2022-06-07 |
| 11314920 | Time-driven placement and/or cloning of components for an integrated circuit | Woohyun Chung, Lakshmi N. Reddy | 2022-04-26 |
| 11301757 | Fault-tolerant power-driven synthesis | Charles J. Alpert, Pallab Datta, Myron D. Flickner, Zhou Li, Dharmendra S. Modha | 2022-04-12 |
| 11120192 | White space insertion for enhanced routability | Hua Xiang, Gustavo E. Tellez, Jennifer KAZDA | 2021-09-14 |
| 11087062 | Dynamic SADP region generation | Hua Xiang, Gustavo E. Tellez | 2021-08-10 |
| 11080443 | Memory element graph-based placement in integrated circuit design | Myung-Chul Kim, Arjen A. Mets, Shyam Ramji, Lakshmi N. Reddy, Alexander J. Suess +2 more | 2021-08-03 |
| 11074379 | Multi-cycle latch tree synthesis | Lakshmi N. Reddy, Gustavo E. Tellez, Paul G. Villarrubia, Christopher J. Berry, Michael H. Wood +2 more | 2021-07-27 |
| 10977419 | Time-driven placement and/or cloning of components for an integrated circuit | Woohyun Chung, Lakshmi N. Reddy | 2021-04-13 |
| 10891411 | Hierarchy-driven logical and physical synthesis co-optimization | David J. Geiger, Paul G. Villarrubia, Shyam Ramji, Myung-Chul Kim, Benjamin Neil Trombley | 2021-01-12 |
| 10831979 | Time-driven placement and/or cloning of components for an integrated circuit | Woohyun Chung, Lakshmi N. Reddy | 2020-11-10 |
| 10796064 | Autonomous placement to satisfy self-aligned double patterning constraints | Hua Xiang, Gustavo E. Tellez, Shyam Ramji | 2020-10-06 |
| 10762271 | Model-based refinement of the placement process in integrated circuit generation | Myung-Chul Kim, Shyam Ramji, Benjamin Neil Trombley, Paul G. Villarrubia | 2020-09-01 |
| 10719656 | Triple and quad coloring of shape layouts | Alexey Y. Lvov, Gustavo E. Tellez | 2020-07-21 |
| 10679120 | Power driven synaptic network synthesis | Charles J. Alpert, Pallab Datta, Myron D. Flickner, Zhuo Li, Dharmendra S. Modha | 2020-06-09 |
| 10635773 | Enhancing stability of half perimeter wire length (HPWL)-driven analytical placement | Myung-Chul Kim, Paul G. Villarrubia, Shyam Ramji, Benjamin Neil Trombley | 2020-04-28 |
| 10606978 | Triple and quad coloring of shape layouts | Alexey Y. Lvov, Gustavo E. Tellez | 2020-03-31 |
| 10558775 | Memory element graph-based placement in integrated circuit design | Myung-Chul Kim, Arjen A. Mets, Shyam Ramji, Lakshmi N. Reddy, Alexander J. Suess +2 more | 2020-02-11 |
| 10552740 | Fault-tolerant power-driven synthesis | Charles J. Alpert, Pallab Datta, Myron D. Flickner, Zhuo Li, Dharmendra S. Modha | 2020-02-04 |