Issued Patents All Time
Showing 1–25 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417333 | Short net pin alignment for routing | Hua Xiang, Benjamin Neil Trombley, Gi-Joon Nam, Gustavo E. Tellez | 2025-09-16 |
| 12282725 | Enhanced alignment for global placement in a circuit | Alexey Y. Lvov, Gi-Joon Nam, Benjamin Neil Trombley, Lakshmi N Reddy | 2025-04-22 |
| 12277375 | Power staple avoidance for routing via reduction | Hua Xiang, Benjamin Neil Trombley, Gi-Joon Nam, Gustavo E. Tellez | 2025-04-15 |
| 11916384 | Region-based power grid generation through modification of an initial power grid based on timing analysis | David Wolpert, Basanth Jagannathan, Michael H. Wood, Leon Sigal, James Leland +2 more | 2024-02-27 |
| 11080456 | Automated design closure with abutted hierarchy | Michael A. Kazda, Harald D. Folberth, Stephan Held, Pietro Saccardi | 2021-08-03 |
| 11080443 | Memory element graph-based placement in integrated circuit design | Myung-Chul Kim, Arjen A. Mets, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy +2 more | 2021-08-03 |
| 11074379 | Multi-cycle latch tree synthesis | Lakshmi N. Reddy, Gustavo E. Tellez, Christopher J. Berry, Michael H. Wood, Robert Alan Philhower +2 more | 2021-07-27 |
| 10891411 | Hierarchy-driven logical and physical synthesis co-optimization | Gi-Joon Nam, David J. Geiger, Shyam Ramji, Myung-Chul Kim, Benjamin Neil Trombley | 2021-01-12 |
| 10803224 | Propagating constants of structured soft blocks while preserving the relative placement structure | Salim A. Shah, Rokesh Jayasundar, Shyam Ramji | 2020-10-13 |
| 10762271 | Model-based refinement of the placement process in integrated circuit generation | Myung-Chul Kim, Gi-Joon Nam, Shyam Ramji, Benjamin Neil Trombley | 2020-09-01 |
| 10685160 | Large cluster persistence during placement optimization of integrated circuit designs | Myung-Chul Kim, Shyam Ramji, Natarajan Viswanathan | 2020-06-16 |
| 10635773 | Enhancing stability of half perimeter wire length (HPWL)-driven analytical placement | Myung-Chul Kim, Shyam Ramji, Gi-Joon Nam, Benjamin Neil Trombley | 2020-04-28 |
| 10558775 | Memory element graph-based placement in integrated circuit design | Myung-Chul Kim, Arjen A. Mets, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy +2 more | 2020-02-11 |
| 10528695 | Integer arithmetic method for wire length minimization in global placement with convolution based density penalty computation | Alexey Y. Lvov, Gi-Joon Nam, Benjamin Neil Trombley, Myung-Chul Kim | 2020-01-07 |
| 10140409 | Large cluster persistence during placement optimization of integrated circuit designs | Myung-Chul Kim, Shyam Ramji, Natarajan Viswanathan | 2018-11-27 |
| 9754062 | Timing adjustments across transparent latches to facilitate power reduction | Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma | 2017-09-05 |
| 9524363 | Element placement in circuit design based on preferred location | Charles J. Alpert, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan | 2016-12-20 |
| 9495501 | Large cluster persistence during placement optimization of integrated circuit designs | Myung-Chul Kim, Shyam Ramji, Natarajan Viswanathan | 2016-11-15 |
| 9483596 | Multi power synthesis in digital circuit design | John T. Badar, David J. Geiger, KM Mozammel Hossain | 2016-11-01 |
| 9098669 | Boundary latch and logic placement to satisfy timing constraints | Charles J. Alpert, Mark D. Aubel, Gregory F. Ford, Zhuo Li, Chin Ngai Sze +1 more | 2015-08-04 |
| 8954915 | Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuit | Yiu-Hing Chan, Mark D. Mayo, Shyam Ramji | 2015-02-10 |
| 8954912 | Structured placement of latches/flip-flops to minimize clock power in high-performance designs | Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Chin Ngai Sze +1 more | 2015-02-10 |
| 8930867 | Scheduling for parallel processing of regionally-constrained placement problem | Gi-Joon Nam, Shyam Ramji, Taraneh Taghavi | 2015-01-06 |
| 8826215 | Routing centric design closure | Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze | 2014-09-02 |
| 8799846 | Facilitating the design of a clock grid in an integrated circuit | Christopher J. Berry, Joseph N. Kozhaya, Daniel R. Menard, Susan R. Sanicky, Amanda Christine Venton +1 more | 2014-08-05 |