Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11157280 | Dynamic fusion based on operand size | Maarten J. Boersma, Bruce M. Fleischer, Balaram Sinharoy | 2021-10-26 |
| 11074379 | Multi-cycle latch tree synthesis | Lakshmi N. Reddy, Gustavo E. Tellez, Paul G. Villarrubia, Christopher J. Berry, Michael H. Wood +2 more | 2021-07-27 |
| 10740104 | Tagging target branch predictors with context with index modification and late stop fetch on tag mismatch | Jentje Leenstra, Nicholas R. Orzol, Christian Zoellin, Michael J. Genden | 2020-08-11 |
| 10579384 | Effective address based instruction fetch unit for out of order processors | Balaram Sinharoy | 2020-03-03 |
| 10552159 | Power management of branch predictors in a computer processor | David S. Levitan, Nicholas R. Orzol | 2020-02-04 |
| 10037207 | Power management of branch predictors in a computer processor | David S. Levitan, Nicholas R. Orzol | 2018-07-31 |
| 9996351 | Power management of branch predictors in a computer processor | David S. Levitan, Nicholas R. Orzol | 2018-06-12 |
| 8255669 | Method and apparatus for thread priority control in a multi-threaded processor based upon branch issue information including branch confidence information | Michael K. Gschwind, Raymond Cheung Yeung | 2012-08-28 |
| 8006070 | Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system | Michael K. Gschwind, Raymond Cheung Yeung | 2011-08-23 |
| 7925853 | Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system | Michael K. Gschwind, Raymond Cheung Yeung | 2011-04-12 |
| 7913070 | Time-of-life counter for handling instruction flushes from a queue | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall, David Shippy | 2011-03-22 |
| 7797521 | Method, system, and computer program product for path-correlated indirect address predictions | Richard J. Eickemeyer, Michael K. Gschwind, Ravi Nair | 2010-09-14 |
| 7725659 | Alignment of cache fetch return data relative to a thread | Michael K. Gschwind, Hans M. Jacobson | 2010-05-25 |
| 7681056 | Dynamic power management in a processor design | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall, David Shippy | 2010-03-16 |
| 7627742 | Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system | Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Michael K. Gschwind, Ravi Nair +2 more | 2009-12-01 |
| 7512772 | Soft error handling in microprocessors | Michael K. Gschwind | 2009-03-31 |
| 7490224 | Time-of-life counter design for handling instruction flushes from a queue | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall, David Shippy | 2009-02-10 |
| 7401242 | Dynamic power management in a processor design | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall, David Shippy | 2008-07-15 |
| 7370176 | System and method for high frequency stall design | Jonathan James DeMent, Kurt A. Feiste, David Shippy | 2008-05-06 |
| 6785703 | Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology | Douglas H. Bradley, Tai Anh Cao | 2004-08-31 |
| 6711633 | 4:2 compressor circuit for use in an arithmetic unit | Douglas H. Bradley, Tai Anh Cao, Wai Yin Wong | 2004-03-23 |
| 6131182 | Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros | Michael P. Beakes, Barbara Alana Chappell, Terry I. Chappell, Gary S. Ditlow, Barry Lee Dorfman +5 more | 2000-10-10 |