Issued Patents All Time
Showing 25 most recent of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11163577 | Selectively supporting static branch prediction settings only in association with processor-designated types of instructions | Sheldon B. Levenstein, Brian W. Thompto | 2021-11-02 |
| 10795683 | Predicting indirect branches using problem branch filtering and pattern cache | Richard J. Eickemeyer, Tejas Karkhanis, Brian R. Konigsburg, Douglas R. G. Logan, Mauricio J. Serrano | 2020-10-06 |
| 10678551 | Operation of a multi-slice processor implementing tagged geometric history length (TAGE) branch prediction | Nicholas R. Orzol | 2020-06-09 |
| 10664279 | Instruction prefetching in a computer processor using a prefetch prediction vector | Richard J. Eickemeyer, Sheldon B. Levenstein, Mauricio J. Serrano | 2020-05-26 |
| 10552162 | Variable latency flush filtering | Glenn O. Kincaid, Albert J. Van Norstrand, Jr. | 2020-02-04 |
| 10552159 | Power management of branch predictors in a computer processor | Nicholas R. Orzol, Robert Alan Philhower | 2020-02-04 |
| 10528352 | Blocking instruction fetching in a computer processor | Bryan G. Hickerson, Sheldon B. Levenstein, Albert J. Van Norstrand, Jr. | 2020-01-07 |
| 10528353 | Generating a mask vector for determining a processor instruction address using an instruction tag in a multi-slice processor | Mehul Patel | 2020-01-07 |
| 10467008 | Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor | Mehul Patel, Albert J. Van Norstrand, Jr., Phillip G. Williams | 2019-11-05 |
| 10379857 | Dynamic sequential instruction prefetching | Richard J. Eickemeyer, Sheldon B. Levenstein, Mauricio J. Serrano, Brian W. Thompto | 2019-08-13 |
| 10353710 | Techniques for predicting a target address of an indirect branch instruction | Richard J. Eickemeyer, Naga P. Gorti, Albert J. Van Norstrand, Jr. | 2019-07-16 |
| 10275256 | Branch prediction in a computer processor | Bruce M. Fleischer, Michael N. Goulet, Nicholas R. Orzol | 2019-04-30 |
| 10248555 | Managing an effective address table in a multi-slice processor | Akash V. Giri, Mehul Patel, Albert J. Van Norstrand, Jr. | 2019-04-02 |
| 10241905 | Managing an effective address table in a multi-slice processor | Akash V. Giri, Mehul Patel, Albert J. Van Norstrand, Jr. | 2019-03-26 |
| 10175987 | Instruction prefetching in a computer processor using a prefetch prediction vector | Richard J. Eickemeyer, Sheldon B. Levenstein, Mauricio J. Serrano | 2019-01-08 |
| 10078514 | Techniques for dynamic sequential instruction prefetching | Richard J. Eickemeyer, Sheldon B. Levenstein, Mauricio J. Serrano, Brian W. Thompto | 2018-09-18 |
| 10037207 | Power management of branch predictors in a computer processor | Nicholas R. Orzol, Robert Alan Philhower | 2018-07-31 |
| 9996351 | Power management of branch predictors in a computer processor | Nicholas R. Orzol, Robert Alan Philhower | 2018-06-12 |
| 9983878 | Branch prediction using multiple versions of history data | Jose E. Moreira, Mauricio J. Serrano | 2018-05-29 |
| 9904551 | Branch prediction using multiple versions of history data | Jose E. Moreira, Mauricio J. Serrano | 2018-02-27 |
| 9898295 | Branch prediction using multiple versions of history data | Jose E. Moreira, Mauricio J. Serrano | 2018-02-20 |
| 9715411 | Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing system | Richard W. Doing, Brian R. Konigsburg, Kevin N. Magill | 2017-07-25 |
| 9524166 | Tracking long GHV in high performance out-of-order superscalar processors | Richard J. Eickemeyer, Tejas Karkhanis, Brian R. Konigsburg, Douglas R. G. Logan, Jose E. Moreira +1 more | 2016-12-20 |
| 9495164 | Branch prediction using multiple versions of history data | Jose E. Moreira, Mauricio J. Serrano | 2016-11-15 |
| 9483271 | Compressed indirect prediction caches | Tejas Karkhanis, Jose E. Moreira, Mauricio J. Serrano | 2016-11-01 |