Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11748104 | Microprocessor that fuses load and compare instructions | Bryan Lloyd, David A. Hrusecky, Sundeep Chadha, Dung Q. Nguyen, Christian Zoellin +2 more | 2023-09-05 |
| 11593108 | Sharing instruction cache footprint between multiple threads | Nicholas R. Orzol, Christian Zoellin, David Campbell | 2023-02-28 |
| 11593109 | Sharing instruction cache lines between multiple threads | Nicholas R. Orzol, Christian Zoellin, David Campbell | 2023-02-28 |
| 11392386 | Program counter (PC)-relative load and store addressing for fused instructions | Nicholas R. Orzol, Christian Zoellin, Brian W. Thompto, Dung Q. Nguyen, Niels Fricke +2 more | 2022-07-19 |
| 11249757 | Handling and fusing load instructions in a processor | Bryan Lloyd, Brian W. Thompto, Dung Q. Nguyen, Brian D. Barrick, Christian Zoellin | 2022-02-15 |
| 11163571 | Fusion to enhance early address generation of load instructions in a microprocessor | Brian D. Barrick, Sundeep Chadha, Phillip G. Williams, Niels Fricke, Dung Q. Nguyen +2 more | 2021-11-02 |
| 11163577 | Selectively supporting static branch prediction settings only in association with processor-designated types of instructions | Brian W. Thompto, David S. Levitan | 2021-11-02 |
| 10983797 | Program instruction scheduling | Christian Zoellin, Phillip G. Williams, Brian W. Thompto, Dung Q. Nguyen, Hung Q. Le +3 more | 2021-04-20 |
| 10664279 | Instruction prefetching in a computer processor using a prefetch prediction vector | Richard J. Eickemeyer, David S. Levitan, Mauricio J. Serrano | 2020-05-26 |
| 10593420 | Testing content addressable memory and random access memory | Harry Barowski, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter | 2020-03-17 |
| 10528352 | Blocking instruction fetching in a computer processor | Bryan G. Hickerson, David S. Levitan, Albert J. Van Norstrand, Jr. | 2020-01-07 |
| 10379857 | Dynamic sequential instruction prefetching | Richard J. Eickemeyer, David S. Levitan, Mauricio J. Serrano, Brian W. Thompto | 2019-08-13 |
| 10175987 | Instruction prefetching in a computer processor using a prefetch prediction vector | Richard J. Eickemeyer, David S. Levitan, Mauricio J. Serrano | 2019-01-08 |
| 10170199 | Testing content addressable memory and random access memory | Harry Barowski, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter | 2019-01-01 |
| 10079070 | Testing content addressable memory and random access memory | Harry Barowski, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter | 2018-09-18 |
| 10078514 | Techniques for dynamic sequential instruction prefetching | Richard J. Eickemeyer, David S. Levitan, Mauricio J. Serrano, Brian W. Thompto | 2018-09-18 |
| 8635408 | Controlling power of a cache based on predicting the instruction cache way for high power applications | David S. Levitan | 2014-01-21 |
| 8549235 | Method for detecting address match in a deeply pipelined processor design | Miles Robert Dooley, Scott Bruce Frommer, David A. Hrusecky | 2013-10-01 |
| 7962722 | Branch target address cache with hashed indices | David S. Levitan, Lixin Zhang | 2011-06-14 |
| 7831775 | System and method for tracking changes in L1 data cache directory | Anthony Saporito | 2010-11-09 |
| 7809924 | System for generating effective address | Rachel Flood, Scott Bruce Frommer, David A. Hrusecky, Michael Thomas Vaden | 2010-10-05 |
| 7788450 | Method and apparatus for efficiently accessing both aligned and unaligned data from a memory | Eric Jason Fluhr | 2010-08-31 |
| 7660965 | Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream | Joaquin Hinojosa, Bruce Joseph Ronchetti | 2010-02-09 |
| 7603543 | Method, apparatus and program product for enhancing performance of an in-order processor with long stalls | Miles Robert Dooley, Scott Bruce Frommer, Hung Q. Le, Anthony Saporito | 2009-10-13 |
| 7571283 | Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch | Scott Bruce Frommer, Bruce Joseph Ronchetti, Anthony Saporito | 2009-08-04 |