SL

Sheldon B. Levenstein

IBM: 52 patents #1,616 of 70,183Top 3%
🗺 Texas: #1,603 of 125,132 inventorsTop 2%
Overall (All Time): #50,728 of 4,157,543Top 2%
52
Patents All Time

Issued Patents All Time

Showing 26–50 of 52 patents

Patent #TitleCo-InventorsDate
7401186 System and method for tracking changes in L1 data cache directory Anthony Saporito 2008-07-15
7380062 Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch Scott Bruce Frommer, Bruce Joseph Ronchetti, Anthony Saporito 2008-05-27
7360058 System and method for generating effective address Rachel Flood, Scott Bruce Frommer, David A. Hrusecky, Michael Thomas Vaden 2008-04-15
7350051 Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream Joaquin Hinojosa, Bruce Joseph Ronchetti 2008-03-25
7318127 Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor David A. Hrusecky, Bruce Joseph Ronchetti, Anthony Saporito 2008-01-08
7302525 Method and apparatus for efficiently accessing both aligned and unaligned data from a memory Eric Jason Fluhr 2007-11-27
7284094 Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class David A. Hrusecky, Bruce Joseph Ronchetti, Anthony Saporito 2007-10-16
7228385 Processor, data processing system and method for synchronizing access to data in shared memory Guy L. Guthrie, William J. Starke, Derek E. Williams 2007-06-05
7200717 Processor, data processing system and method for synchronizing access to data in shared memory Guy L. Guthrie, William J. Starke, Derek E. Williams 2007-04-03
7197604 Processor, data processing system and method for synchronzing access to data in shared memory Guy L. Guthrie, William J. Starke, Derek E. Williams 2007-03-27
7092270 Apparatus and method for detecting multiple hits in CAM arrays Michael Ju Hyeok Lee, Edelmar Seewann 2006-08-15
6567839 Thread switch control in a multithreaded processor system John Michael Borkenhagen, Richard J. Eickemeyer, William T. Flynn, Andrew Henry Wottreng 2003-05-20
6557084 Apparatus and method to improve performance of reads from and writes to shared memory locations Donald Lee Freerksen, Gary Lippert 2003-04-29
6205063 Apparatus and method for efficiently correcting defects in memory circuits Anthony Gus Aipperspach 2001-03-20
6138209 Data processing system and multi-way set associative cache utilizing class predict data structure and method thereof David J. Krolak 2000-10-24
6105051 Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor John Michael Borkenhagen, Richard J. Eickemeyer, William T. Flynn, Steven R. Kunkel, Andrew Henry Wottreng 2000-08-15
6088788 Background completion of instruction and associated fetch request in a multithread processor John Michael Borkenhagen, Richard J. Eickemeyer, Andrew Henry Wottreng, Duane A. Averill, James Ira Brookhouser 2000-07-11
5897662 Pseudo-random address generation mechanism that reduces address translation time Michael J. Corrigan, Terrence James Stewart 1999-04-27
5812521 Static adder using BICMOS emitter dot circuits Nghia V. Phan 1998-09-22
5790838 Pipelined memory interface and method for using the same John D. Irish, Charles L. Johnson, David J. Krolak 1998-08-04
5751990 Abridged virtual address cache directory David J. Krolak, Lyle Edwin Grosbach, John D. Irish 1998-05-12
5586331 Duplicated logic and interconnection system for arbitration among multiple information processors 1996-12-17
5566305 Duplicated logic and interconnection system for arbitration among multiple information processors 1996-10-15
5463741 Duplicated logic and interconnection system for arbitration among multiple information processors 1995-10-31
5339397 Hardware primary directory lock Richard G. Eikill, Lynn A. McMahon, Joseph P. Weigel 1994-08-16