| 9235521 |
Cache system for managing various cache line conditions |
Judy M. Gehman, Scott E. Greenfield, Jerome M. Meyer, John M. Nystuen |
2016-01-12 |
| 8924779 |
Proxy responder for handling anomalies in a hardware system |
George Wayne Nation, Srinivasa Rao Kothamasu |
2014-12-30 |
| 8095734 |
Managing cache line allocations for multiple issue processors |
Judy M. Gehman, John M. Nystuen |
2012-01-10 |
| 7496861 |
Method for generalizing design attributes in a design capture environment |
George Wayne Nation, Gary S. Delp |
2009-02-24 |
| 7340700 |
Method for abstraction of manufacturing test access and control ports to support automated RTL manufacturing test insertion flow for reusable modules |
Steven Emerson, Jonathan Byrn, Donald Gabrielson |
2008-03-04 |
| 7157948 |
Method and apparatus for calibrating a delay line |
Gary McClannahan, Daniel Paul Wetzel |
2007-01-02 |
| 6871267 |
Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency |
Donald Lee Freerksen |
2005-03-22 |
| 6823431 |
Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency |
Donald Lee Freerksen |
2004-11-23 |
| 6557084 |
Apparatus and method to improve performance of reads from and writes to shared memory locations |
Donald Lee Freerksen, Sheldon B. Levenstein |
2003-04-29 |
| 6467032 |
Controlled reissue delay of memory requests to reduce shared memory address contention |
— |
2002-10-15 |
| 6351791 |
Circuit arrangement and method of maintaining cache coherence utilizing snoop response collection logic that disregards extraneous retry responses |
Donald Lee Freerksen, Farnaz Mounes-Toussi |
2002-02-26 |
| 6314491 |
Peer-to-peer cache moves in a multiprocessor data processing system |
Donald Lee Freerksen, John D. Irish |
2001-11-06 |
| 6260117 |
Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency |
Donald Lee Freerksen |
2001-07-10 |
| 6065098 |
Method for maintaining multi-level cache coherency in a processor with non-inclusive caches and processor implementing the same |
— |
2000-05-16 |
