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Jonathan Byrn — 46 Patents

LSLsi: 28 patents #59 of 3,238Top 2%

IBM: 18 patents #6,142 of 70,183Top 9%

Rochester, MN: #119 of 3,042 inventorsTop 4%

Minnesota: #1,025 of 52,454 inventorsTop 2%

Overall (All Time): #62,001 of 4,157,543Top 2%

46 Patents All Time

Jonathan Byrn has been granted 46 US patents while listed as an inventor at Lsi. The first was granted in 1993 and the most recent in June 2013. Jonathan Byrn ranks #62,001 of 4,157,543 US inventors in our database (top 1.5%). Patent records list Jonathan Byrn in Rochester, MN, US.

Patents per Year

Issued Patents All Time

Showing 1–25 of 46 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
8471720	On-chip power supply monitoring using a network of modulators	Mark F. Turner, Jeffrey S. Brown	2013-06-25
8415714	Programmable nanotube interconnect	—	2013-04-09
8336018	Power grid optimization	Mark F. Turner, Jeffrey S. Brown	2012-12-18
8209573	Sequential element low power scan implementation	Jeff S. Brown, Mark F. Turner	2012-06-26
8196086	Granular channel width for power optimization	Jeffrey S. Brown, Mark F. Turner	2012-06-05
8135976	Modulated clock, an IC including the modulated clock and a method of providing a modulated clock signal for power control	Jeff S. Brown, Mark F. Turner, Paul Dorweiler	2012-03-13
8017512	Efficient power management method in integrated circuit through a nanotube structure	—	2011-09-13
7966592	Dual path static timing analysis	Jeffrey S. Brown, Mark F. Turner	2011-06-21
7847285	Configurable power segmentation using a nanotube structure	—	2010-12-07
7818695	Redistribution of current demand and reduction of power and DCAP	Mark F. Turner, Jeffrey S. Brown	2010-10-19	$2,752,000
7787325	Row decode driver gradient design in a memory device	Jeffrey S. Brown, Mark F. Turner	2010-08-31	$4,227,000
7755111	Programmable power management using a nanotube structure	—	2010-07-13	$3,929,000
7703059	Method and apparatus for automatic creation and placement of a floor-plan region	Daniel James Murray	2010-04-20	$6,107,000
7655548	Programmable power management using a nanotube structure	—	2010-02-02	$4,085,000
7494842	Programmable nanotube interconnect	—	2009-02-24	$3,472,000
7496867	Cell library management for power optimization	Mark F. Turner, Jeffrey S. Brown	2009-02-24	$3,472,000
7430725	Suite of tools to design integrated circuits	Robert Neal Carlton Broberg, III, Gary S. Delp, Michael K. Eneboe, Gary McClannahan, George Wayne Nation +3 more	2008-09-30	$4,674,000
7412678	Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design	Juergen Lahner, Srinivas Adusumalli	2008-08-12	$28,313,000
7380229	Automatic generation of correct minimal clocking constraints for a semiconductor product	Matthew Wingren	2008-05-27	$6,448,000
7340700	Method for abstraction of manufacturing test access and control ports to support automated RTL manufacturing test insertion flow for reusable modules	Steven Emerson, Donald Gabrielson, Gary Lippert	2008-03-04	$8,518,000
7290224	Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit	Grant Lindberg	2007-10-30	$7,228,000
7263678	Method of identifying floorplan problems in an integrated circuit layout	Daniel James Murray	2007-08-28	$11,601,000
7149218	Cache line cut through of limited life data in a data processing system	Chad B. McBride, Robert Neal Carlton Broberg, III, Gary McClannahan	2006-12-12	$11,904,000
7103858	Process and apparatus for characterizing intellectual property for integration into an IC platform environment	Robert M. Biglow	2006-09-05	$4,267,000
7055113	Simplified process to design integrated circuits	Robert Neal Carlton Broberg, III, Gary S. Delp, Michael K. Eneboe, Gary McClannahan, George Wayne Nation +3 more	2006-05-30	$4,983,000