Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411729 | Energy-efficient error-correction-detection storage | Frederick A. Ware, John Eric Linstadt | 2025-09-09 |
| 12347479 | Command-triggered data clock distribution mode | Ian Shaeffer, Lei Luo | 2025-07-01 |
| 12347480 | Memory system with multiple open rows per bank | Thomas Vogelsang, John Eric Linstadt | 2025-07-01 |
| 12346567 | Partial array refresh timing | Thomas Vogelsang, John Eric Linstadt | 2025-07-01 |
| 12230355 | Hierarchical bank group timing | John Eric Linstadt, Thomas Vogelsang | 2025-02-18 |
| 12072817 | Flash memory device having a calibration mode | Pravin Kumar Venkatesan, Kashinath Prabhu, Makarand Ajit Shirasgaonkar | 2024-08-27 |
| 12050513 | Energy-efficient error-correction-detection storage | Frederick A. Ware, John Eric Linstadt | 2024-07-30 |
| 11972121 | Load-reduced DRAM stack | Thomas Vogelsang | 2024-04-30 |
| 11955161 | Command-triggered data clock distribution mode | Ian Shaeffer, Lei Luo | 2024-04-09 |
| 11921650 | Dedicated cache-related block transfer in a memory system | — | 2024-03-05 |
| 11868619 | Partial array refresh timing | Thomas Vogelsang, John Eric Linstadt | 2024-01-09 |
| 11842761 | Memory system with multiple open rows per bank | Thomas Vogelsang, John Eric Linstadt | 2023-12-12 |
| 11829307 | DRAM interface mode with interruptible internal transfer operation | Frederick A. Ware, Brent Haukness | 2023-11-28 |
| 11829308 | Flash memory device having a calibration mode | Pravin Kumar Venkatesan, Kashinath Prabhu, Makarand Ajit Shirasgaonkar | 2023-11-28 |
| 11803489 | Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling | Pravin Kumar Venkatesan, Kashinath Prabhu, Makarand Ajit Shirasgaonkar | 2023-10-31 |
| 11782863 | Memory module with configurable command buffer | Ian Shaeffer, Yi Lu | 2023-10-10 |
| 11675657 | Energy-efficient error-correction-detection storage | Frederick A. Ware, John Eric Linstadt | 2023-06-13 |
| 11599483 | Dedicated cache-related block transfer in a memory system | — | 2023-03-07 |
| 11587605 | Command-triggered data clock distribution | Ian Shaeffer, Lei Luo | 2023-02-21 |
| 11526632 | Securing address information in a memory controller | Craig E. Hampel, John Eric Linstadt, Steven C. Woo | 2022-12-13 |
| 11372795 | Memory with alternative command interfaces | Ian Shaeffer, Yi Lu | 2022-06-28 |
| 11372784 | Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling | Pravin Kumar Venkatesan, Kashinath Prabhu, Makarand Ajit Shirasgaonkar | 2022-06-28 |
| 11327831 | Energy-efficient error-correction-detection storage | Frederick A. Ware, John Eric Linstadt | 2022-05-10 |
| 11232047 | Dedicated cache-related block transfer in a memory system | — | 2022-01-25 |
| 11226909 | DRAM interface mode with interruptible internal transfer operation | Frederick A. Ware, Brent Haukness | 2022-01-18 |