Issued Patents All Time
Showing 1–25 of 159 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411781 | Memory system with cached memory module operations | Frederick A. Ware, Kenneth L. Wright, Craig E. Hampel | 2025-09-09 |
| 12411729 | Energy-efficient error-correction-detection storage | Frederick A. Ware, Liji Gopalakrishnan | 2025-09-09 |
| 12412603 | Flexible metadata allocation and caching | Taeksang Song, Steven C. Woo, Craig E. Hampel | 2025-09-09 |
| 12394500 | Memory system with error detection | Frederick A. Ware | 2025-08-19 |
| 12375109 | Integration of compression algorithms with error correction codes | Thomas Vogelsang, Michael Alexander Hamburg, Evan Lawrence Erickson | 2025-07-29 |
| 12347480 | Memory system with multiple open rows per bank | Thomas Vogelsang, Liji Gopalakrishnan | 2025-07-01 |
| 12346567 | Partial array refresh timing | Liji Gopalakrishnan, Thomas Vogelsang | 2025-07-01 |
| 12346198 | Selectable multi-stage error detection and correction | Evan Lawrence Erickson | 2025-07-01 |
| 12321234 | Energy efficient storage of error-correction-detection information | Michael Raymond Miller, Stephen Magee | 2025-06-03 |
| 12321502 | Integrity and data encryption (IDE) buffer device with low-latency containment mode | Evan Lawrence Erickson | 2025-06-03 |
| 12306711 | Dynamically configurable memory error control schemes | Craig E. Hampel | 2025-05-20 |
| 12306716 | Error coalescing | — | 2025-05-20 |
| 12298842 | Memory module register access | Thomas J. Giovannini, Catherine Chen, Scott C. Best, Frederick A. Ware | 2025-05-13 |
| 12298926 | High-performance, high-capacity memory systems and modules | Frederick A. Ware, Ely Tsern, Thomas J. Giovannini, Craig E. Hampel, Scott C. Best +1 more | 2025-05-13 |
| 12237255 | Vertical interconnects with variable pitch for scalable escape routing | Mark D. Kellam | 2025-02-25 |
| 12230355 | Hierarchical bank group timing | Liji Gopalakrishnan, Thomas Vogelsang | 2025-02-18 |
| 12229435 | Memory component with input/output data rate alignment | Frederick A. Ware, Torsten Partsch | 2025-02-18 |
| 12222829 | Memory module with dedicated repair devices | Frederick A. Ware, Brent Haukness, Scott C. Best | 2025-02-11 |
| 12213548 | Hybrid memory module | Frederick A. Ware, Kenneth L. Wright | 2025-02-04 |
| 12210467 | Memory modules and systems with variable-width data ranks and configurable data-rank timing | Thomas J. Giovannini, Catherine Chen | 2025-01-28 |
| 12135645 | Nonvolatile physical memory with DRAM cache | Frederick A. Ware, Christopher Haywood | 2024-11-05 |
| 12105975 | Adjustable access energy and access latency memory system and devices | Frederick A. Ware | 2024-10-01 |
| 12050513 | Energy-efficient error-correction-detection storage | Frederick A. Ware, Liji Gopalakrishnan | 2024-07-30 |
| 12040035 | Buffer circuit with adaptive repair capability | Scott C. Best, Paul William Roukema | 2024-07-16 |
| 12032845 | Memory controller partitioning for hybrid memory system | Frederick A. Ware | 2024-07-09 |