Issued Patents All Time
Showing 1–25 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12386763 | Protocol including selective output by memory of a timing reference signal | Ian Shaeffer | 2025-08-12 |
| 12314162 | Circuits and methods for self-adaptive decision-feedback equalization in a memory system | Andrew M. Fuller, Barry William Daly, Lei Luo, Masum Hossain | 2025-05-27 |
| 12298926 | High-performance, high-capacity memory systems and modules | Frederick A. Ware, Ely Tsern, John Eric Linstadt, Craig E. Hampel, Scott C. Best +1 more | 2025-05-13 |
| 12298842 | Memory module register access | Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware | 2025-05-13 |
| 12210467 | Memory modules and systems with variable-width data ranks and configurable data-rank timing | John Eric Linstadt, Catherine Chen | 2025-01-28 |
| 12141081 | Training and operations with a double buffered memory topology | Chi-Ming Yeung, Yoshie Nakabayashi, Henry Stracovsky | 2024-11-12 |
| 12136452 | Method and apparatus for calibrating write timing in a memory system | Alok Gupta, Ian Shaeffer, Steven C. Woo | 2024-11-05 |
| 12062413 | Signal receiver with skew-tolerant strobe gating | Andrew M. Fuller, Robert E. Palmer, Michael D. Bucher, Thoai-Thai Le | 2024-08-13 |
| 11953981 | Memory module register access | Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware | 2024-04-09 |
| 11949539 | Burst-tolerant decision feedback equalization | Abhijit Abhyankar | 2024-04-02 |
| 11907139 | Memory system design using buffer(s) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Henry Stracovsky | 2024-02-20 |
| 11815940 | Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules | Frederick A. Ware, Ely Tsern, John Eric Linstadt, Kenneth L. Wright | 2023-11-14 |
| 11816047 | Protocol including a command-specified timing reference signal | Ian Shaeffer | 2023-11-14 |
| 11809345 | Data-buffer component with variable-width data ranks and configurable data-rank timing | John Eric Linstadt, Catherine Chen | 2023-11-07 |
| 11768780 | Training and operations with a double buffered memory topology | Chi-Ming Yeung, Yoshie Nakabayashi, Henry Stracovsky | 2023-09-26 |
| 11763865 | Signal receiver with skew-tolerant strobe gating | Andrew M. Fuller, Robert E. Palmer, Michael D. Bucher, Thoai-Thai Le | 2023-09-19 |
| 11755508 | High-performance, high-capacity memory systems and modules | Frederick A. Ware, Ely Tsern, John Eric Linstadt, Craig E. Hampel, Scott C. Best +1 more | 2023-09-12 |
| 11682448 | Method and apparatus for calibrating write timing in a memory system | Alok Gupta, Ian Shaeffer, Steven C. Woo | 2023-06-20 |
| 11573849 | Memory module register access | Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware | 2023-02-07 |
| 11537540 | Memory system design using buffer(s) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Henry Stracovsky | 2022-12-27 |
| 11404103 | Method and apparatus for calibrating write timing in a memory system | Alok Gupta, Ian Shaeffer, Steven C. Woo | 2022-08-02 |
| 11341070 | Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules | Frederick A. Ware, Ely Tsern, John Eric Linstadt, Kenneth L. Wright | 2022-05-24 |
| 11294830 | Training and operations with a double buffered memory topology | Chi-Ming Yeung, Yoshie Nakabayashi, Henry Stracovsky | 2022-04-05 |
| 11289139 | Memory components and controllers that calibrate multiphase synchronous timing references | Scott C. Best, Lei Luo, Ian Shaeffer | 2022-03-29 |
| 11275702 | Memory module and registered clock driver with configurable data-rank timing | John Eric Linstadt, Catherine Chen | 2022-03-15 |