Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12141081 | Training and operations with a double buffered memory topology | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2024-11-12 |
| 11907139 | Memory system design using buffer(s) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2024-02-20 |
| 11768780 | Training and operations with a double buffered memory topology | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2023-09-26 |
| 11537540 | Memory system design using buffer(s) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2022-12-27 |
| 11294830 | Training and operations with a double buffered memory topology | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2022-04-05 |
| 11003601 | Memory system design using buffer(s) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2021-05-11 |
| 10613995 | Training and operations with a double buffered memory topology | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2020-04-07 |
| 10614002 | Memory system design using buffer(S) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2020-04-07 |
| 10169258 | Memory system design using buffer(s) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2019-01-01 |
| 9043674 | Error detection and correction apparatus and method | Wei Wu, Shih-Lien Linus Lu, Rajat Agarwal | 2015-05-26 |
| 8495464 | Reliability support in memory systems without error correcting code support | Michael Espig, Victor W. Lee, Daehyun Kim | 2013-07-23 |
| 6587894 | Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time based in part on characterization data specific to memory | Piotr Szabelski | 2003-07-01 |
| 6539440 | Methods and apparatus for prediction of the time between two consecutive memory accesses | Piotr Szabelski | 2003-03-25 |
| 6532505 | Universal resource access controller | Piotr Szabelski | 2003-03-11 |
| 6510474 | Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests | Piotr Szabelski | 2003-01-21 |
| 6453370 | Using of bank tag registers to avoid a background operation collision in memory systems | Piotr Szabelski | 2002-09-17 |
| 6442644 | Memory system having synchronous-link DRAM (SLDRAM) devices and controller | David Gustavson, David V. James, Hans A. Wiggers, Peter B. Gillingham, Cormac Michael O'Connell +9 more | 2002-08-27 |
| 6442666 | Techniques for improving memory access in a virtual memory system | — | 2002-08-27 |
| 6430642 | Methods and apparatus for prioritization of access to external devices | Piotr Szabelski | 2002-08-06 |
| 6385708 | Using a timing-look-up-table and page timers to determine the time between two consecutive memory accesses | Piotr Szabelski | 2002-05-07 |
| 6378049 | Universal memory controller | Piotr Szabelski | 2002-04-23 |
| 6374323 | Computer memory conflict avoidance using page registers | Piotr Szabelski | 2002-04-16 |
| 6286075 | Method of speeding up access to a memory page using a number of M page tag registers to track a state of physical pages in a memory device having N memory banks where N is greater than M | Piotr Szabelski | 2001-09-04 |
| 6216178 | Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution | Piotr Szabelski | 2001-04-10 |
| 6195724 | Methods and apparatus for prioritization of access to external devices | Piotr Szabelski | 2001-02-27 |